M30622MA-XXXFP RENESAS [Renesas Technology Corp], M30622MA-XXXFP Datasheet - Page 153

• Manufacturer Part Number: M30622MA-XXXFP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY
• Manufacturer: RENESAS [Renesas Technology Corp]

Clock asynchronous serial I/O (UART) mode
138
Figure 1.19.22. Typical transmit/receive timing in UART mode (used for the SIM interface)
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
TxD
RxD
Transmit register
empty flag (TXEPT)
RxD
TxD
Signal conductor level
(Note)
Receive complete
flag (RI)
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Signal conductor level
(Note 2)
Transmit interrupt
request bit (IR)
Transfer clock
Receive enable
bit (RE)
Receive interrupt
request bit (IR)
Note: Equal in waveform because TxD
2
2
2
2
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
The above timing applies to the following settings :
Shown in ( ) are bit symbols.
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”.
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Start
ST
ST
Start
ST
ST
bit
bit
D
D
D
D
0
0
0
0
Data is set in UART2 transmit buffer register
D
D
D
D
2
1
1
1
1
Tc
and RxD
Tc
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
2
4
4
4
4
are connected.
D
D
D
D
5
5
5
5
D
D
Transferred from UART2 transmit buffer register to UART2 transmit register
D
D
6
6
6
6
D
D
D
Parity
D
Parity
7
7
7
7
bit
bit
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi
Tc = 16 (n + 1) / fi
P
P
P
P
Cleared to “0” when interrupt request is accepted, or cleared by software
SP
SP
SP
SP
fi : frequency of BRG2 count source (f
n : value set to BRG2
fi : frequency of BRG2 count source (f
n : value set to BRG2
Stop
Stop
bit
bit
Read to receive buffer
ST
ST
The level is detected by the
interrupt routine.
ST
ST
Note 1
A “L” level returns from TxD
the occurrence of a parity error.
A “L” level returns from TxD
the occurrence of a parity error.
D
D
D
D
0
0
0
0
D
D
D
D
1
1
1
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
4
4
4
4
D
D
1
D
D
1
5
, f
5
, f
2
5
5
2
8
due to
8
D
D
, f
D
due to
, f
D
6
6
6
6
32
32
D
D
D
)
)
D
7
7
7
7
P
P
P
P
Read to receive buffer
Mitsubishi microcomputers
SP
M16C / 62 Group
SP
SP
SP
The level is
detected by the
interrupt routine.