M30622MA-XXXFP RENESAS [Renesas Technology Corp], M30622MA-XXXFP Datasheet - Page 508

• Manufacturer Part Number: M30622MA-XXXFP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY
• Manufacturer: RENESAS [Renesas Technology Corp]

Interrupt
Figure 4.2.3. The timing of reflecting the change in the I flag to the interrupt
4.2.1 Interrupt Enable Flag
4.2.2 Interrupt Request Bit
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
The content is changed when the I flag is changed causes the acceptance of the interrupt request in the
following timing:
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
When changed by FCLR, FSET, POPC, or LDC instruction
When changed by REIT instruction
Interrupt request generated
Interrupt request generated
• When changing the I flag using the REIT instruction, the acceptance of the interrupt takes
• When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the
effect as the REIT instruction is executed.
acceptance of the interrupt is effective as the next instruction is executed.
(If I flag is changed from 0 to 1 by REIT instruction)
(If I flag is changed from 0 to 1 by FSET instruction)
instruction
instruction
Previous
Previous
FSET I
REIT
Determination whether or not to
accept interrupt request
Interrupt sequence
Next instruction
Determination whether or not to
accept interrupt request
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Time
Interrupt sequence
Mitsubishi microcomputers
M16C / 62 Group
Time
493