M30622MA-XXXFP RENESAS [Renesas Technology Corp], M30622MA-XXXFP Datasheet - Page 364

• Manufacturer Part Number: M30622MA-XXXFP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY
• Manufacturer: RENESAS [Renesas Technology Corp]

UART
Table 2.5.2. Example of baud rate setting
Table 2.5.3. Error detection
Framing error
Parity error
Error-sum flag
Overrun error
(2) Transfer rate
Baud rate
(3) An error detection
Type of error
(bps)
The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans-
fer rate. The count source for the transfer rate register can be selected from f
from the CLK pin. Clocks f
respectively.
In clock-asynchronous serial I/O mode, detect errors are shown in Table 2.5.3.
14400
19200
28800
31250
1200
2400
4800
9600
600
count source
BRG's
f
f
f
f
f
f
f
f
f
• With parity enabled, this error
• This error occurs when the
• The next data is written to the
• The UARTi receive interrupt
• This error occurs when the
• This flag turns on when any
8
8
8
1
1
1
1
1
1
occurs when the total number
of 1's in character bits and the
parity bit is different from the
specified number.
next data lines up before the
content of the UARTi receive
buffer register is read.
UARTi receive buffer register.
request bit does not go to “1”.
stop bit falls short of the set
number of stop bits.
error (overrun, framing, or
parity) is detected.
Description
1
BRG's set value : n
, f
8
, f
207 (CF
207 (CF
103 (67
103 (67
31 (1F
51 (33
68 (44
51 (33
34 (22
32
System clock : 16MHz
are derived by dividing the CPU’s main clock by 1, 8, and 32
16
16
16
16
16
16
16
16
16
)
)
)
)
)
)
)
)
)
Actual time (bps)
When the flag turns on
The error is detected
when data is
transferred from the
UARTi receive register
to the UARTi receive
buffer register.
14493
19231
28571
31250
1202
2404
4808
9615
601
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BRG's set value : n
95 (5F
47 (2F
95 (5F
47 (2F
31 (1F
15 (F
23 (17
23 (17
• Set the serial I/O mode select
• Set the receive enable bit to
• Set the serial I/O mode select
• Set the receive enable bit to
• Read the lower-order byte of
• When all error (overrun,
System clock : 7.3728MHz
bits to “000
“0”.
framing, and parity) are
removed, the flag is cleared.
bits to ”000
“0”.
the UARTi receive buffer
register.
16
16
16
16
16
16
16
16
How to clear the flag
)
)
)
)
)
)
)
)
1
, f
8
, f
2
2
Mitsubishi microcomputers
”.
”.
M16C / 62 Group
32
Actual time (bps)
, and the input
14400
19200
28800
1200
2400
4800
9600
600
349