AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet

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AM79C971VCW

Manufacturer Part Number

AM79C971VCW

Description

PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus

Manufacturer

Advanced Micro Devices

Datasheet

1.AM79C971VCW.pdf (265 pages)

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Am79C971

PCnet™-FAST

Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus

DISTINCTIVE CHARACTERISTICS

Single-chip Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) local

bus

— 32-bit glueless PCI host interface

— Supports PCI clock frequency from DC to

— Supports network operation with PCI clock

— High performance bus mastering

— PCI specification revision 2.1 compliant

— Supports PCI Subsystem/Subvendor ID/

— Supports both PCI 5.0-V and 3.3-V signaling

— Plug and Play compatible

— Supports an unlimited PCI burst length

— Big endian and little endian byte alignments

Integrated 10BASE-T and 10BASE-2/5 (AUI)

Physical Layer Interface

— Single-chip IEEE/ANSI 802.3, IEC/ISO 8802-3

— Automatic Twisted-Pair receive polarity

— Internal 10BASE-T transceiver with Smart

— IEEE 802.3-compliant auto-negotiable

Supports General Purpose Serial Interface

(GPSI)

Media Independent Interface (MII) for

connecting external 10- or 100-Megabit per

second (Mbps) transceivers

— IEEE 802.3-compliant MII

— Intelligent Auto-Poll™ external PHY status

33 MHz independent of network clock

from 15 MHz to 33 MHz

architecture with integrated Direct Memory

Access (DMA) Buffer Management Unit for

low CPU and bus utilization

Vendor ID programming through the

EEPROM interface

environments

supported

and Blue Book Ethernet-compliant solution

detection and correction

Squelch to Twisted-Pair medium

10BASE-T interface

monitor and interrupt

— Includes intelligent on-chip Network Port

— Supports both auto-negotiable and non

— Supports 10BASE-T, 100BASE-TX/FX,

Internal/external loopback capabilities on all

ports

Supports patented External Address Detection

Interface (EADI)

— Receive frame tagging support for inter-

Dual-speed CSMA/CD (10 Mbps and 100 Mbps)

Media Access Controller (MAC) compliant with

IEEE/ANSI 802.3 and Blue Book Ethernet

standards

Full-duplex operation supported in AUI,

10BASE-T, MII, and GPSI ports with

independent Transmit (TX) and Receive (RX)

channels

Flexible buffer architecture

— Large independent internal TX and RX FIFOs

— SRAM-based FIFO buffer extension

— 1/2 Gigabit per second (Gbps) internal data

— Programmable FIFO watermarks for both TX

— RX frame queuing for high latency PCI bus

— Programmable allocation of buffer space

EEPROM interface supports jumperless design

and provides through-chip programming

— Supports full programmability of half-/full-

Extensive LED status support

Manager that provides auto-port selection

between MII, on-chip 10BASE-T port, and AUI

without software support

auto-negotiable external PHYs

100BASE-T4, and 100BASE-T2 IEEE 802.3-

compliant MII PHYs at full- or half-duplex

networking applications

supporting up to 128 kilobytes (Kbytes)

bandwidth

and RX operations

host operation

between RX and TX queues

duplex operation for external 100 Mbps PHYs

through EEPROM mapping

Publication# 20550

Issue Date: May 2000

Rev: E Amendment: /0

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