AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 169

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

1
EEDET Value
(BCR19[13])
ESK
0
0
1
1
Connected?
and PREAD = 0 and ECS is set to
a 1, then the EECS pin will be
forced to a HIGH level at the ris-
ing edge of the next clock follow-
ing bit programming.
EEPROM Serial Clock. This bit
and the EDI/EDO bit are used to
control host access to the EE-
PROM. Values programmed to
this bit are placed onto the EESK
pin at the rising edge of the next
clock following bit programming,
except when the PREAD bit is set
to 1 or the EEN bit is set to 0. If
both the ESK bit and the EDI/
EDO bit values are changed dur-
ing one BCR19 write operation,
while EEN = 1, then setup and
If EEN = 1 and PREAD = 0 and
ECS is set to a 0, then the EECS
pin will be forced to a LOW level
at the rising edge of the next
clock following bit programming.
ECS has no effect on the output
value of the EECS pin unless the
PREAD bit is set to 0 and the
EEN bit is set to 1.
Read accessible always, write
accessible only when either the
STOP or the SPND bit is set.
ECS is set to 0 by H_RESET and
is not affected by S_RESET or
STOP.
EEPROM
Yes
Yes
No
No
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
Result if PREAD is Set to 1
P R E L I M I N A R Y
Table 34. EEDET Setting
Am79C971
0
EDI/EDO
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
failure will result, PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur, checksum
operation will pass, PVALID is set to 1.
Result of Automatic EEPROM Read
Operation Following H_RESET
hold times of the EEDI pin value
with respect to the EESK signal
edge are not guaranteed.
ESK has no effect on the EESK
pin unless the PREAD bit is set to
0 and the EEN bit is set to 1.
Read accessible always, write
accessible only when either the
STOP or the SPND bit is set. ESK
is reset to 1 by H_RESET and is
not affected by S_RESET or
STOP.
Data Out. Data that is written to
this bit will appear on the EEDI
output of the interface, except
when the PREAD bit is set to 1 or
the EEN bit is set to 0. Data that
is read from this bit reflects the
value of the EEDO input of the in-
terface.
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit is
set to 0 and the EEN bit is set to
1.
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set. EDI/
EDO is reset to 0 by H_RESET
and is not affected by S_RESET
or STOP.
EEPROM Data In/ EEPROM
169