AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 36

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

Master Bus Interface Unit
The master Bus Interface Unit (BIU) controls the acqui-
sition of the PCI bus and all accesses to the initializa-
tion block, descriptor rings, and the receive and
transmit buffer memory. Table 3 shows the usage of
PCI commands by the Am79C971controller in master
mode.
36
C[3:0]
0000
0001
0010
0011
0100
0101
0110
Interrupt
Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Table 3. Master Commands
Command
DEVSEL
FRAME
PERR
TRDY
IRDY
C/BE
CLK
PAR
AD
Figure 10. Slave Cycle Data Parity Error Response
Not used
Not used
Not used
Not used
Read of the initialization
block and descriptor
rings
Read of the transmit
buffer in non-burst mode
1
2
Use
ADDR
CMD
3
PAR
4
Am79C971
DATA
5
BE
Bus Acquisition
The Am79C971microcode will determine when a DMA
transfer should be initiated. The first step in any
Am79C971bus master transfer is to acquire ownership
of the bus. This task is handled by synchronous logic
within the BIU. Bus ownership is requested with the
REQ signal and ownership is granted by the arbiter
through the GNT signal.
C[3:0]
0111
1000
1001
1010
1011
1100
1101
1110
1111
6
PAR
Table 3. Master Commands (Continued)
7
Memory Write
Reserved
Reserved
Configuration Read Not used
Configuration Write Not used
Memory Read
Multiple
Dual Address Cycle Not used
Memory Read Line
Memory Write
Invalidate
Command
8
9
10
Write to the descriptor
rings and to the receive
buffer
Read of the transmit
buffer in burst mode
Read of the transmit
buffer in burst mode
Not used
Use
20550D-13