AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 148

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

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IPG
Note: Programming of the IPG
should be done in nibble intervals
instead of absolute bit times. The
decimal and hex values do not
match due to delays in the part
used to make up the final IPG.
Changes should be added or sub-
tracted from the provided hex val-
ue on a one-for-one basis.
Reserved locations. Written as
zeros and read as undefined.
Inter Packet Gap. Changing IPG
allows the user to program the
Am79C971 controller for aggres-
siveness on a network. By chang-
ing the default value of 96 bit
times (6oh) the user can adjust
the fairness or aggressiveness of
the Am79C971 MAC on the net-
work. By programming a lower
number of bit times other then the
ISO/IEC 8802-3 standard re-
quires, the Am79C971 MAC will
become more aggressive on the
network. This aggressive nature
will give rise to the Am79C971
controller possibly “capturing the
network” at times by forcing other
less aggressive nodes to defer.
By programming a larger number
of bit times, the Am79C971 MAC
will become less aggressive on
the network and may defer more
often than normal. The perfor-
mance of the Am79C971 control-
ler may decrease as the IPG
value is increased from the de-
fault value.
CAUTION: Use this parameter
with care. By lowering the IPG
below the ISO/IEC 8802-3 stan-
dard
Am79C971 controller can inter-
rupt normal network behavior.
Read accessible always. Write
accessible when the STOP bit is
set to 1. IPG is set to 60h (96 Bit
times)
S_RESET and is not affected by
STOP.
96
by
bit
H_RESET
times,
P R E L I M I N A R Y
the
Am79C971
or
7-0
Bus Configuration Registers
The Bus Configuration Registers (BCR) are used to
program the configuration of the bus interface and
other special features of the Am79C971 controller that
are not related to the IEEE 8802-3 MAC functions. The
BCRs are accessed by first setting the appropriate
RAP value and then by performing a slave access to
the BDP. See Table 30.
All BCR registers are 16 bits in width in Word I/O mode
(DWIO = 0, BCR18, bit 7) and 32 bits in width in DWord
I/O mode (DWIO = 1). The upper 16 bits of all BCR reg-
isters is undefined when in DWord I/O mode. These
bits should be written as zeros and should be treated
as undefined when read. The default value given for
any BCR is the value in the register after H_RESET.
Some of these values may be changed shortly after
H_RESET when the contents of the external EEPROM
is automatically read in. None of the BCR register val-
ues are affected by the assertion of the STOP bit.
IFS1
InterFrameSpacingPart1. Chang-
ing IFS1 allows the user to pro-
gram the value of the InterFrame-
SpacePart1
Am79C971 controller sets the de-
fault value at 60 bit times (3ch).
See the subsection on Medium
Allocation in the section Media
Access Management for more
details. The equation for setting
IFS1 when IPG
IFS1 = IPG - 36 bit times
Note: Programming of the IPG
should be done in nibble intervals
instead of absolute bit times due
to the MII. The decimal and hex
values do not match due to de-
lays in the part used to make up
the final IPG.
Changes should be added or
subtracted from the provided hex
value on a one-for-one basis.
Due to changes in synchroniza-
tion delays internally through dif-
ferent network ports, the IFS1
can be off by as much as +12 bit
times.
Read accessible always. Write
accessible only when the SPND
bit or the STOP bit is set to 1.
IFS1 is set to 3ch (60 bit times) by
H_RESET or S_RESET and is
not affected by STOP.
timing.
96 bit times is:
The