AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 85

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

The time that the Am79C971 controller waits for data to
be valid is programmable. ROMTMG (BCR18, bits 15-
12) defines the time from when the Am79C971 control-
ler drives EBUA_EBA[7:0] with the lower 8 bits of the
Expansion ROM address to when the Am79C971 con-
troller latches in the data on the EBD[7:0] inputs. The
register value specifies the time in number of clock cy-
cles. When ROMTMG is set to nine (the default value),
EBD[7:0] is sampled with the next rising edge of CLK
ten clock cycles after EBUA_EBA[7:0] was driven with
a new address value. The clock edge that is used to
sample the data is also the clock edge that generates
the next Expansion ROM address. All four bytes of Ex-
pansion ROM data are stored in holding registers. One
clock cycle after the last data byte is available, the
Am79C971 controller asserts TRDY.
The access time for the Expansion ROM device (tACC)
can be calculated by subtracting the clock-to-output
delay for the EBUA_EBA[7:0] outputs (tv_A_D) and the
input-to-clock setup time for the EBD[7:0] inputs (ts_D)
from the time defined by ROMTMG:
Figure 42. SRAM and Flash Configuration for the Expansion Bus
Am79C971
EBUA_EBA[7:0]
EBDA[15:8]
AS_/EBOE
EROMCS
ERAMCS
EBD[7:0]
EBWE
Am79C971
D-FF
'374
tACC
For an adapter card application, the value used for
clock period should be 30 ns to guarantee correct inter-
face timing at the maximum clock frequency of 33 MHz.
The timing diagram in Figure 45 assumes the default
programming of ROMTMG (1001b = 9 CLK). After
reading the first byte, the Am79C971 controller reads in
three more bytes by incrementing the lower portion of
the ROM address. After the last byte is strobed in,
TRDY will be asserted on clock 50. When the host tries
to perform a burst read of the Expansion ROM, the
Am79C971 controller will disconnect the access at the
second data phase.
The host must program the Expansion ROM Base Ad-
dress register in the PCI configuration space before the
first access to the Expansion ROM. The Am79C971
controller will not react to any access to the Expansion
ROM until both MEMEN (PCI Command register, bit 1)
and ROMEN (PCI Expansion ROM Base Address reg-
ister, bit 0) are set to 1.
ROMTMG* clock period - tv_A_D - ts_D
I/O[7:0]
A[14:8]
A[7:0]
WE
CS
OE
I/O[7:0]
A[14:8]
A[7:0]
WE
CS
OE
A[23:16]
A[15:8]
A[7:0]
WE
DQ[7:0]
CS
OE
32K x 8 SRAM
32K x 8 SRAM
FLASH
20550D-45
85