AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 199

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AM79C971VCW

Manufacturer Part Number
AM79C971VCW
Description
PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
Manufacturer
Advanced Micro Devices
Datasheet
AM79C971 BUS CONFIGURATION REGISTERS (CONTINUED)
20
21
22
25
26
27
29
30
31
32
33
34
SWSTYLE
INTCON
PCILAT
SRAMSIZE
SRAMBND
SRAMIC
EPADDRL
EPADDRU
EBDATA
STVAL
MIICAS
MIIADDR
MIIMDR
Software Style (DEFAULT = 0000, maps to CSR 58)
Interrupt Control
8000
4000
2000
1000
PCI Latency (DEFAULT = FF06)
bits [15:8] = MAX_LAT
bits [7:0] = MIN_GNT
SRAM Size (DEFAULT = 000)
bits [7:0] = SRAM_SIZE
SRAM Boundary (DEFAULT = 0000)
bits [7:0] = SRAM_BND
SRAM Interface Control
8000
4000
bits [5:3] = EBCS, Expansion Bus Clock Source
bits [2:0] = CLK_FAC, Expansion Bus Clock Factor
Expansion Port Address Lower
Expansion Port Address Upper
8000
4000
2000
1000
Expansion Bus Data Port
Software Timer Interrupt Value (DEFAULT = FFFF)
MII Status and Control (DEFAULT = 0400)
8000
4000
2000
1000
MII Address
bits [9:5] = PHYAD, Physical Layer Device Address
bits [4:0] = REGAD, MII/Auto-Negotiation Register Address
MII Data Port
--
--
--
--
PTR TST
LOLATRX
0000
0008
0010
0000
0001
0002
0003
FLASH
AINC
--
--
ANTST
MIIPD
FMDC1
FMD0
0800--
0400--
0200--
0100--
0800
0400
0200
0100
0800
0400
0200
0100
CLK pin, PCI clock (external clock not required)
XTAL1 and XTAL2 pins, 20 MHz clock (external clock not required)
EBCLK pin, Expansion Bus Clock (external clock not required)
1/1 clock factor
1/2 clock factor
--
--
Am79C971
--
--
--
--
APEP
APDW2
APDW1
APDW0
0080--
0040--
0020--
0010--
0080
0040
0020
0010
0080
0040
0020
0010
XPHYANE
DANAS
XPHYRST
XPHYFD
--
--
--
--
0008--
0004--
0002--
0001--
0008
0004
0002
0001
0008
0004
0002
0001
EPADDRU3
EPADDRU2
EPADDRU1
EPADDRU0
XPHYSP
MII L
MIILP
FCON
199

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