AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 41

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

Disconnect Without Data Transfer
Figure 17 shows a target disconnect sequence during
which no data is transferred. STOP is asserted on clock
4 without TRDY being asserted at the same time. The
Am79C971 controller terminates the access with the
deassertion of FRAME on clock 5 and of IRDY one
clock cycle later. It finally releases the bus on clock 7.
The Am79C971 controller will again request the bus
after two clock cycles to retry the last transfer. The
starting address of the new transfer will be the address
of the last non-transferred data.
Target Abort
Figure 18 shows a target abort sequence. The target
asserts DEVSEL for one clock. It then deasserts
DEVSEL and asserts STOP on clock 4. A target can
use the target abort sequence to indicate that it can-
not service the data transfer and that it does not want
the transaction to be retr ied. Additionally, the
Am79C971 controller cannot make any assumption
DEVSEL
FRAME
TRDY
STOP
IRDY
C/BE
REQ
GNT
CLK
PAR
AD
DEVSEL is sampled
1
Figure 16. Disconnect With Data Transfer
2
ADDR i
0111
3
DATA
PAR
4
0000
Am79C971
DATA
5
PAR
about the success of the previous data transfers in the
current transaction. The Am79C971 controller termi-
nates the current transfer with the deassertion of
FRAME on clock 5 and of IRDY one clock cycle later.
It finally releases the bus on clock 6.
Since data integrity is not guaranteed, the Am79C971
controller cannot recover from a target abort event. The
Am79C971 controller will reset all CSR locations to
their STOP_RESET values. The BCR and PCI config-
uration registers will not be cleared. Any on-going net-
wor k transmission is ter minated in an order ly
sequence. If less than 512 bits have been transmitted
onto the network, the transmission will be terminated
immediately, generating a runt packet. If 512 bits or
more have been transmitted, the message will have the
current FCS inverted and appended at the next byte
boundary to guarantee an FCS error is detected at the
receiving station.
6
7
8
9
10
ADDR i +8
0111
11
20550D-19
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