AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 93

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

SRAM Accesses
The SRAM access during normal operations is a single
cycle address load to fill the upper bits into the ‘374 fol-
lowed by 17 subsequent accesses. This results in the
best utilization for the 4-FIFO arbiter in the Am79C971
controller. If the FIFO does not have enough data to
complete the full 18 cycles, the arbiter will switch after
all of the data has been written or read. This under uti-
lization occurs only at the end of a packet.
The most significant address byte EBUA_EBA[7:0] is
registered into the external ‘374 by asser tion of
EBUA_EBA[7:0]
Figure 51. Block Diagram Low Latency Receive Configuration
AS_EBOE
EBD[15:0]
ERAMCS
Interface
PCI Bus
Management
EBCLK
Unit
EBWE
Buff er
Unit
Figure 52. Typical SRAM Read Operation
1
15:8
2
7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0
3
FIFO
FIFO
4
Bus
Rcv
Bus
Xmt
Expansion Bus Interface
5
Am79C971
6
Contr ol
FIFO
7
8
AS_EBOE The least significant address byte is then
toggled on the EBUA_EBA[7:0] throughout the remain-
der of the read/write access. The data word is made up
of the most significant data byte EBDA[15:8], and the
least significant data byte EBD[7:0]. ERAMCS is con-
nected to the CE/CS chip select of the external SRAM.
AS_EBOE provides the output enable signal to the
SRAM during read operations. During write operations,
the AS_EBOE is driven high during the remainder of
the accesses. EBWE is toggled during SRAM writes.
See Figure 52 and Figure 53.
9
MAC
FIFO
MAC
FIFO
Rcv
Xmt
10
7:0
11
7:0 7:0 7:0 7:0 7:0 7:0 7:0
12 13 14 15 16 17 18
802.3
Core
MAC
20550D-55
20550D-54
93