AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 120

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

120
STP = 1, then some descriptors/
buffers may be skipped in the
ring. While performing the search
for the next STP bit that is set to
1, the Am79C971 controller will
advance through the receive de-
scriptor ring regardless of the
state of ownership bits. If any of
the entries that are examined
during
Am79C971 controller ownership
of the descriptor but also indicate
STP = 0, then the Am79C971
controller will reset the OWN bit
to 0 in these entries. If a scanned
entry indicates host ownership
with
Am79C971 controller will not al-
ter the entry, but will advance to
the next entry.
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
the Am79C971 controller, then
the Am79C971 controller will stop
advancing through the ring en-
tries and begin periodic polling of
this entry. When the STP bit is
found to be true, and the descrip-
tor that contains this setting is
owned by the Am79C971 control-
ler, then the Am79C971 control-
ler will stop advancing through
the ring entries, store the descrip-
tor information that it has just
read, and wait for the next re-
ceive to arrive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
header portion of a receive pack-
et will always be written to a par-
ticular memory area, and the data
portion of a receive packet will al-
ways be written to a separate
memory area. The interrupt is
generated when the header bytes
have been written to the header
memory area.
Read/Write accessible always.
The LAPPEN bit will be reset to 0
by H_RESET or S_RESET and
will be unaffected by STOP.
STP = 0,
this
search
then
indicate
the
Am79C971
4
3
2
DXMT2PD Disable Transmit Two Part Defer-
EMBA
BSWP
See Appendix D for more infor-
mation on the Look Ahead Pack-
et Processing concept.
Read/Write accessible always.
DXMT2PD
H_RESET or S_RESET and is
not affected by STOP.
Read/Write accessible always.
EMBA is cleared by H_RESET or
S_RESET and is not affected by
STOP.
When big Endian mode is select-
ed, the Am79C971 controller will
swap the order of bytes on the AD
bus during a data phase on ac-
cesses to the FIFOs only. Specif-
ically, AD[31:24] becomes Byte
0, AD[23:16] becomes Byte 1,
AD[15:8] becomes Byte 2, and
AD[7:0] becomes Byte 3 when
big Endian mode is selected.
When little Endian mode is se-
lected, the order of bytes on the
AD bus during a data phase is:
AD[31:24] is Byte 3, AD[23:16] is
Byte 2, AD[15:8] is Byte 1, and
AD[7:0] is Byte 0.
Byte swap only affects data
transfers that involve the FIFOs.
Initialization block transfers are
not affected by the setting of the
ral (see Medium Allocation sec-
tion
Management section for more
details). If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
rithm (see Contention Resolution
section in Media Access Man-
agement section for more de-
tails). If EMBA is set, a modified
back-off algorithm is implement-
ed.
choose between big and little En-
dian modes of operation. When
BSWP is set to a 1, big Endian
mode is selected. When BSWP is
set to 0, little Endian mode is se-
lected.
Enable Modified Back-off Algo-
Byte Swap. This bit is used to
in
the
is
Media
cleared
Access
by