AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 253

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

Am79C971A PCnet-FAST 10/100 Mbps PCI
Ethernet Controller REV A.6 ERRATA
REV A.6 STATUS
Revision A.6 silicon is the current full production silicon. Rev. A.6 has fixed rev. A.5 errata #13, #17 and #18. With
revision A.6, the device part number has also been revised to Am79C971A in order to distinguish it from revision
A.5 (Am79C971).
REV A.6 ERRATA SUMMARY
The device has seventeen errata to date. The system-level impact of these errata on customers is minimal. All infor-
mation below should be used in conjunction with the Am79C971 PCnet-FAST preliminary data sheet, dated March
1999 (PID #20550D). This datasheet applies to all revisions of the PCnet-FAST device. These errata do not affect
operation with PCnet software drivers.
Important Note: In 100 Mb mode, the Am79C971A requires the use of SRAM. Additionally, the SRAM clock
(EBCLK) should be driven with a 33 MHz clock, or if pulled up, the PCI clock should be 33MHz.
PCNET-FAST REV. A.6 ERRATA
The Symptom section gives an external description of the problem. The Implication section explains how the device
behaves and its impact on the system. The WORK AROUND section describes a work around for the problem. The
status section indicates when and how the problem will be fixed.
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3)
Symptom: The default Inter Packet Gap (IPG) value of 60H in CSR125, bits 15-8, results in an actual IPG of
100 bit-times versus the expected 96 bit-times.
Implication: There is a 4 bit-time offset between the IPG value in CSR125 and the actual IPG at the AUI,
10BASE-T, and MII ports of the PCnet-FAST device.
Workaround: Write the value 5CH into the IPG field of CSR125 to ensure an actual, minimum IPG of 96 bit-
times.
Status: No current plan to fix this erratum.
Symptom: The Interrupt Request pin (INTA#, pin 142), and some of the analog pins (RXD-, pin 110, RXD+,
pin 111, TXP-, pin 113, TXD-, pin 114, XTAL2, pin 120, DO-, pin 122, DI-, pin 125, DI+, pin 126, CI-, pin 127,
CI+, pin 128) are not accessible through the IEEE 1149.1 (JTAG) test interface.
Implication: Those pins are not included in the boundary-scan chain within the device.
Workaround: None.
Status: No current plan to fix this erratum.
Symptom: At high temperature and low Vcc (85 °C, 4.75V) with a minimum PCI clock low time of 12 ns, the
Tval timing for some PCI interface signals exceeds the PCI spec (11 ns max.) by up to 3 ns. The measured
value is less than 14 ns maximum on the production tester for this specific corner case for FRAME# de-asser-
tion, STOP# assertion, PERR# de-assertion, and DEVSEL# assertion.
Implication: Tval timing is well within the PCI spec for nominal Vcc and 50/50 PCI clock duty cycle. Typical
PCI systems should be able to tolerate Tval timings of 14 ns.
Workaround: None.
Status: No current plan to fix this erratum.
APPENDIX F
F-1