AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 98

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

circuitry will remain active even while the SLEEP pin is
driven LOW. All other sections of the device are shut
down except the LED0 pin, the only LED pin that con-
tinues to function, just as in normal operation. The
LNKSTE bit must be set in BCR4 to enable indication
of a good 10BASE-T link if there are link beat pulses or
valid frames present. Once the T-MAU has a good link,
LED0 will be active. This LED0 pin can be used to drive
an LED and/or external hardware that directly controls
the SLEEP pin of the Am79C971 controller. In the case
of driving external hardware, it can be used to tell an
external SLEEP control logic to drive the SLEEP pin
HIGH to bring the Am79C971 controller out of the
snooze mode. This configuration effectively wakes the
system when there is any activity on the 10BASE-T
link. Snooze mode can be used only if the T-MAU is the
selected network port. Link beat pulses are not trans-
mitted during snooze mode.
SLEEP must not be asserted while the Am79C971
controller is requesting the bus or while a bus cycle is
active. It is recommended to set the Am79C971 con-
troller into suspend mode (SPND (CSR5, bit 0) set to 1)
or to stop the device (STOP (CSR0, bit 2) set to 1) be-
fore asserting the SLEEP pin.
Before the sleep mode is invoked, the Am79C971 con-
troller will perfor m an inter nal S_RESET. This
S_RESET operation will not affect the values of the
BCR registers or the PCI configuration space.
S_RESET terminates all network activity abruptly. The
host can use the suspend mode (SPND, CSR5, bit 0)
to terminate all network activity in an orderly sequence
before issuing an S_RESET.
When coming out of the sleep mode, the Am79C971
controller can be programmed to generate an interrupt
and infor m the dr iver about the wake-up. The
Am79C971 controller will set SLPINT (CSR5, bit 9),
when coming out of the sleep mode. INTA will be as-
serted, when the enable bit SLPINTE (CSR5, bit 8) is
set to 1. Note that the assertion of INTA due to SLPINT
is not dependent on the main interrupt enable bit INEA
(CSR0, bit 6), which will be cleared by the reset going
into the sleep mode.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the as-
sertion of SLEEP until three clock cycles after comple-
tion of a hardware reset operation.
Magic Packet Mode
Magic Packet mode is enabled by performing three
steps. First, the Am79C971 controller must be put into
suspend mode (see description of CSR5, bit 0), allow-
ing any current network activity to finish. Next, MP-
MODE (CSR5, bit 1) must be set to 1 if it has not been
set already. Finally, either SLEEP must be asserted
(hardware control) or MPEN (CSR5, bit 2) must be set
98
Am79C971
to 1 (software control). Note that FASTSPNDE (CSR7,
bit 15) has no meaning in Magic Packet mode.
In Magic Packet mode, the Am79C971 controller re-
mains fully powered up (all VDD and VDDB pins must
remain at their supply levels). The device will not gen-
erate any bus master transfers. No transmit operations
will be initiated on the network. The device will continue
to receive frames from the network, but all frames will
be automatically flushed from the receive FIFO. Slave
accesses to the Am79C971 controller are still possible.
The Magic Packet mode can be disabled at any time by
deasserting SLEEP or clearing MPEN.
A Magic Packet frame is a frame that is addressed to
the Am79C971 MAC and contains a data sequence in
its data field made up of 16 repetitions of the physical
addresses (PADR[47:0]). The Am79C971 controller will
search incoming frames until it finds a Magic Packet
frame. It starts scanning for the sequence after pro-
cessing the length field of the frame. The data se-
quence can begin anywhere in the data field of the
frame, but must be detected before the Am79C971
controller reaches the frame’s FCS field. Any deviation
of the incoming frame’s data sequence from the re-
quired physical address sequence, even by a single bit,
will prevent the detection of that frame as a Magic
Packet frame.
The Am79C971 controller supports two different
modes of address detection for a Magic Packet frame.
If MPPLBA (CSR5, bit 5) is at its default value of 0, the
Am79C971 controller will only detect a Magic Packet
frame if the destination address of the frame matches
the content of the physical address register (PADR). If
MPPLBA is set to 1, the destination address of the
Magic Packet frame can be unicast, multicast or broad-
cast. Note that the setting of MPPLBA only effects the
address detection of the Magic Packet frame. The
Magic Packet frame’s data sequence must be made up
o f 1 6 r e p e t i t i o n s o f t h e p hy s i c a l a d d r e s s e s
(PADR[47:0]), regardless of what kind of destination
address it has.
When the Am79C971 controller detects a Magic
Packet frame, it sets MPINT (CSR5, bit 4) to 1. If INEA
(CSR0, bit 6) and MPINTE (CSR5, bit 3) are set to 1,
INTA will be asserted. The interrupt signal can be used
wake up the system. As an alternative, one of the four
LED pins can be programmed to indicated that a Magic
Packet frame has been received. MPSE (BCR4-7, bit
9) must be set to 1 and the RCVE (BCR4-7, bit 2) must
be set to 0 to enable that function. Note that the polarity
of the LED pin can be programmed to be active high by
setting LEDPOL (BCR4-7, bit 14) to 1.
O n c e a M a gi c Pa cket fr am e i s d e t ec te d , t h e
Am79C971 controller will discard the frame internally,
but will not resume normal transmit and receive opera-
tions until SLEEP is deasserted, or MPEN is cleared,