AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 69

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

T-MAU Loopback Modes
When T-MAU is the active network port there are four
modes of loopback operation: internal loopback with
and without MENDEC and two external loopback
modes.
When INTL and MENDECL are set to 1, internal loop-
back without MENDEC is selected. Data coming out of
the transmit FIFO is fed directly to the receive FIFO.
The T-MAU does not transmit any data to the network,
but it continues to send link pulses. All signals on the
receive inputs are ignored. LCAR (TMD2, bit 27) will al-
ways read zero, regardless of the link state. The pro-
gramming of TMAULOOP has no effect.
When INTL is set to 1 and MENDECL is cleared to 0,
internal loopback including the MENDEC is selected.
Data is routed from the transmit FIFO through the
MENDEC back to the receive FIFO. The T-MAU does
not transmit any data to the network, but it continues to
send link pulses. All signals on the receive inputs are
ignored. LCAR (TMD2, bit 27) will always read zero, re-
gardless of the link state. The programming of TMAU-
LOOP has no effect.
External loopback operation works slightly different
when the T-MAU is the active network port. In a
10BASE-T network, the hub does not generate a re-
ceive carrier back to the Am79C971 controller while the
chip is transmitting. The T-MAU provides this function
internally. A true external loopback covering all the
components on the printed circuit board can only be
performed by using a special connector (with pin 1 jum-
pered to pin 3 and pin 2 jumpered to pin 6) that con-
nects the transmit pins of the RJ-45 jack to its receive
pins. When INTL is cleared to 0 and TMAULOOP is set
to 1, data is transmitted to the network and is expected
to be routed back to the chip. Collision detection is dis-
abled in this mode. The link state machine is forced into
the link pass state. LCAR will always read zero. The
programming of MENDECL has no effect in this mode.
The Am79C971 Am79C971 controller provides a spe-
cial external loopback mode that allows the device to
be connected to a live 10BASE-T network. The virtual
external loopback mode is invoked by setting INTL and
TMAULOOP to 0. In this mode, data coming out of the
transmit FIFO is fed directly into the receive FIFO. Ad-
ditionally, all transmit data is output to the network. The
link state machine is active as is the collision detection
logic. The programming of MENDECL has no effect in
this mode.
Media Independent Interface Loopback Features
Loopback through the MII can be handled in two ways.
The Am79C971 controller supports an internal MII
loopback and an external MII loopback. The MII loop-
back is completely separate from other network port
loopback and requires that the other loopback modes
be disengaged while the MII loopback is running. Fur-
Am79C971
ther, the MII loopback requires that the MII port be
manually configured through software using ASEL
(BCR 2, bit 1) and PORTSEL (CSR 15, bits 8-7).
The external loopback through the MII requires a two-
step operation. The external PHY must be placed into
a loopback mode by writing to the MII Control Register
(BCR33, BCR34). Then the Am79C971 controller must
be placed into an external loopback mode. All other
loopback modes have no meaning during MII opera-
tion.
The internal loopback through the MII is controlled by
MIIILP (BCR32, bit 1). When set to 1, this bit will cause
the internal portion of the MII data port to loopback on
itself. The MII management port (MDC, MDIO) is unaf-
fected by the MIILP bit. The internal MII interface is
mapped in the following way:
During the internal loopback, the TXD, TX_CLK, and
TX_EN pins will toggle appropriately with the correct
data.
Miscellaneous Loopback Features
All transmit and receive function programming, such as
automatic transmit padding and receive pad stripping,
operates identically in loopback as in normal operation.
Loopback mode can be performed with any frame size
except in the MII loopback mode. Runt Packet Accept
is internally enabled (RPA bit in CSR124 is not af-
fected) when any loopback mode is invoked. This is to
be backwards compatible to the C-LANCE (Am79C90)
software.
Since the Am79C971 controller has two FCS genera-
tors, there are no more restrictions on FCS generation
or checking, or on testing multicast address detection
as they exist in the half-duplex PCnet family devices
and in the C-LANCE. On receive, the Am79C971 con-
troller now provides true FCS status. The descriptor for
a frame with an FCS error will have the FCS bit (RMD1,
bit 27) set to 1. The FCS generator on the transmit side
can still be disabled by setting DXMTFCS (CSR15, bit
3) to 1.
In internal loopback operation, the Am79C971 control-
ler provides a special mode to test the collision logic.
When FCOLL (CSR15, bit 4) is set to 1, a collision is
forced during every transmission attempt. This will re-
sult in a Retry error.
The TXD[3:0] nibble data path is looped back onto
the RXD[3:0] nibble data path;
TX_CLK is looped back as RX_CLK;
TX_EN is looped back as RX_DV.
CRS is correctly OR’d with TX_EN and RX_DV and
always encompasses the transmit frame.
TX_ER is not driven by the Am79C971 and there-
fore not looped back.
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