UPD61052 NEC, UPD61052 Datasheet - Page 32

• Manufacturer Part Number: UPD61052
• Description: MPEG2 Audio / Video Encoder
• Manufacturer: NEC

2.5
CPU sends and receives command status through the System Interface Register, which is in the host CPU interface
unit. In addition, to control an internal DMA controller through the system interface register, it loads an instruction for
internal CPU to the instruction RAM and the transfer of the large-volume data can be sent to the data area on SDRAM.
(1) Parallel interface
(2) Serial interface
32
The connection of the host CPU can select the eight bits parallel data interface and serial interface (SPI). Internal
The following describes loading of internal CPU instruction.
When parallel interface is selected, host interface has 6-bit address, 8-bit data bus and control ports.
CWAIT is selected with CMODE1 to wait on ready signal mode, CMODE1 selects active polarity of CWAIT.
The
host CPU becomes a bus master.
The low edge of the chip selection is communication beginning. Its high edge is communication ending.
An address and the reading / writing mode are shown at the first byte after the chip selection becomes low.
It is the MSB first of six bits of addresses, eight bits of data. Fix CSCLK to high level during CCS is disabled (high
level).
The
Host CPU Interface
CSCLK:
CSDI:
CSDO:
CCS:
µ
µ
PD61051/61052 communicates with the host CPU using the SPI (serial peripheral interface) serial bus. The
PD61051/61052 becomes a master and downloads the instruction of the internal CPU from external ROM.
The serial clock
The data input
The data output
The chip selection
Host
CPU
Interface
Register
System
Figure 2-12. Host CPU Interface
Data Sheet S15082EJ4V0DS
µPD61051/61052
Internal CPU
Instruction
Controller
RAM of
DMA
Interface
SDRAM
Internal
CPU
SDRAM
µ
PD61051, 61052