UPD61052 NEC, UPD61052 Datasheet - Page 59

• Manufacturer Part Number: UPD61052
• Description: MPEG2 Audio / Video Encoder
• Manufacturer: NEC

4.6
the internal CPU and restarts.
When changing a mode, host CPU transfers the instruction of each mode from SDRAM to the instruction RAM of
Operation Mode Setting by Changing Firmware
Software reset of internal CPU
Internal CPU reset is canceled
Reset register (3EH) ← 02H
Destination address register
Transfer ending (refer to 4.7)
Number of transfer bytes/4
SDRAM → iRAM transfer
Transfer counter register
Source address register
Transfer mode register
(20H) ← 20H setting
(21H to 23H) setting
(24H to 26H) setting
(27H to 29H) setting
(3EH)←00H setting
Parameter setting
Reset register
Mode setting
Return
N
Data Sheet S15082EJ4V0DS
Host CPU → SDRAM transfer
Interrupt register 0 (30H)←
Destination address register
Interrupt register 0 (30H)
Interrupt register 0 clear
System interface register
Number of transfer bytes
Transfer counter register
Transfer mode register
(30H): (02H or 01H)
Transfer data register
(24H to 26H) setting
(27H to 29H) setting
(20H) ← 40H setting
Interrupt register 0
(3FH) ← Parameter
Parameter setting
writing ending?
writing ending?
All parameters
128 bytes
setting
CINT?
Y
Y
N
Y
Mode setting A
N
N
Y
Transfer ending (refer to 4.7)
Transfer error handling
Interrupt register 0
writing ending?
All parameters
(refer to 4.8)
in SDRAM
(30H): 04H
Return
Return
Y
Y
µ
PD61051, 61052
N
N
Mode setting A
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