UPD61052 NEC, UPD61052 Datasheet - Page 48

• Manufacturer Part Number: UPD61052
• Description: MPEG2 Audio / Video Encoder
• Manufacturer: NEC

3.2.6
3.2.7
48
31H
32H
33H
34H
3EH
Address
Address
31H to
34H
It is set for 1 when the interrupt factor occurs.
The interrupt bit clears when host CPU writes 1 in the bit of the interrupt after the interrupt processing.
When the other interrupt (which isn't masked) is set to 1 when clearing a interrupt, CINT becomes high 1
The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H.
Clear processing continues until interrupt registers is cleared.
Address
When the host CPU sets 1 to ALL RESET, it resets the inside and it returns to 0 automatically.
The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H.
Interrupt register
Reset register
7 to 2
1
0
7 to 0
Bit7
Bit7
Bit
Bit
Bit6
Bit6
NBR
ALL RESET
Field
Field
Bit5
Bit5
Reserved (Set 0)
Internal CPU reset
0: Normal, 1: Reset
Same hardware reset
0: Normal, 1: Reset
Defined by firmware
Defined by firmware
Defined by firmware
Defined by firmware
Bit4
Firmware define
0: Normal, 1: Interrupt
Bit4
Data Sheet S15082EJ4V0DS
Bit3
Bit3
Function
Bit2
Bit2
Function
NBR
Bit1
Bit1
RESET
ALL
Bit0
Bit0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
µ
0
0
PD61051, 61052
Initial value
Interrupt1
Interrupt2
Interrupt3
Interrupt4
Reset
0H
Initial value
µ
s later.