UPD61052 NEC, UPD61052 Datasheet - Page 62

• Manufacturer Part Number: UPD61052
• Description: MPEG2 Audio / Video Encoder
• Manufacturer: NEC

4.8.2
and SDRAM → instruction RAM of internal CPU transfer)
62
This is a error handling of DMA-ERR which occurs when interrupting the transfers (SDRAM read during executing
Transfer error handling 2
Host CPU → SDRAM transfer
Host CPU → SDRAM transfer
Destination address register
(27H to 29H) ← 04H setting
(27H to 29H) ← 04H setting
Interrupt register 0 (30H)
Transfer counter register
Transfer counter register
← Unusing area setting
Transfer mode register
Transfer mode register
(3FH) ← Dummy data
Transfer data register
(20H) ← 02H setting
(20H) ← 00H setting
Clear transfer error
writing ending?
← 04H setting
Transfer error
(24H to 26H)
handling 2
All data
release
Y
N
Interrupt register 0 (30H) setting
SDRAM → host CPU transfer
Data Sheet S15082EJ4V0DS
SDRAM→ host CPU transfer
Clear Interrupt register 0
Interrupt register 0 (30H)←
Transfer mode register
Transfer mode register
Transfer data register
(30H) ← 01H setting
(20H) ← 00H setting
(20H) ← 01H setting
(3FH) → Data read
Interrupt register 0
Interrupt register 0
Interrupt register 0
reading ending?
(30H): 02 H
(30H): 01H
All data
release
CINT?
CINT?
Y
Y
Y
Y
Y
N
N
N
N
N
Host CPU → SDRAM transfer
Host CPU → SDRAM transfer
Destination address register
(27H to 29H) ← 04H setting
Transfer counter register
← Unusing area setting
Transfer mode register
Transfer mode register
(3FH) ← Dummy data
Transfer data register
(30H) ← 01H setting
(20H) ← 02H setting
(20H) ← 00H setting
Interrupt register 0
Interrupt register 0
writing ending?
(24H to 26H)
(30H): 01H
All data
release
Return
CINT?
Y
Y
Y
µ
PD61051, 61052
N
N
N