UPD61052 NEC, UPD61052 Datasheet - Page 45

• Manufacturer Part Number: UPD61052
• Description: MPEG2 Audio / Video Encoder
• Manufacturer: NEC

SDRAM read
<1> Interrupt mask
<2> Set source address
<3> Set the number (equal to or less than 128 bytes) of the data to read by 4 bytes unit
<4> Set the transfer of SDRAM → host CPU.
<5> CINT interrupt (Interrupt pin)
<6> Confirms that the interrupt factor and clear interrupt factor
<7> Data read
<8> CINT interrupt (Interrupt pin)
<9> Confirm the interrupt factor
<10> Release of SDRAM → host CPU mode
<11> Release of interrupt mask
Host CPU sets mask bit to interrupt mask register (2CH to 2FH) for the interrupt that needs a data transfer.
Host CPU sets the address of SDRAM to the source address register (21H to 23H) of the
Host CPU sets the data number of the bytes to the transfer data counter register (27H to 29H) of the
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Host CPU sets 01H to the transfer mode register (20H) of the
Host CPU confirms that the interrupt register 0 (30H) of the
writing a same value of the interrupt register 0 (30H) to the interrupt register 0 (30H) of the
Host CPU reads data from the number of times with the set number of bytes, the transfer data register (3FH) of
the
Host CPU confirms that the interrupt register 0 (30H) of the
interrupt factor in 01H at the interrupt register 0 (30H) register of the
PD61051/61052.
Host CPU clears a writing interrupt factor in 01H at the interrupt register 0 (30H) register of the
after setting 00H to the transfer mode register (20H) of the
It releases the limitation on interrupt which set by <1>.
µ
PD61051/61052.
Data Sheet S15082EJ4V0DS
µ
µ
PD61051/61052.
µ
µ
PD61051/61052 becomes 01H. (It clears a writing
PD61051/61052.
PD61051/61052 becomes 02H or 01H and clears
µ
PD61051/61052.)
µ
PD61051, 61052
µ
µ
PD61051/61052.
PD61051/61052.
µ
PD61051/61052
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