UPD61052 NEC, UPD61052 Datasheet - Page 40

• Manufacturer Part Number: UPD61052
• Description: MPEG2 Audio / Video Encoder
• Manufacturer: NEC

3.2
3.2.1
The original value of the other register is unsettled. It keeps a setting value before reset.
3.2.2
of internal CPU, SDRAM → iRAM of internal CPU and instruction ROM → iRAM of internal CPU.
transfer counter register is changed before releasing the transfer mode register following transfer completion after
setting the transfer mode register and starting the transfer. When transferring data as follows: host CPU → instruction
RAM of internal CPU, host CPU → SDRAM, SDRAM → instruction RAM of internal CPU, instruction ROM → SDRAM,
instruction ROM → instruction RAM of internal CPU, execute a software reset of the internal CPU (address 3EH ←
02H) before transfer and release the reset after transfer.
40
00H to 1FH
Address
Each firmware defines these registers.
These registers are used to communicate with host CPU and internal CPU.
For the details of the register, refer to the application notebook.
The reset of the RESET pin or ALL RESET of the reset register initializes addresses 00H and 01H addresses to 0H.
These registers are defined data transfer such as host CPU → SDRAM, SDRAM → host CPU, host CPU → iRAM
The host CPU transfers with SDRAM via had a transfer buffer of 128 bytes on this LSI.
The transfer with the instruction RAM becomes 4 bytes.
A transfer error occurs if the transfer mode register, source address register, destination address register, or
Register Functions
Common register
Data transfer register
Bit7
Bit6
Bit5
Defined by firmware
Bit4
Data Sheet S15082EJ4V0DS
Bit3
Bit2
Bit1
Bit0
R/W
R/W
µ
PD61051, 61052