UPD61052 NEC, UPD61052 Datasheet - Page 47

• Manufacturer Part Number: UPD61052
• Description: MPEG2 Audio / Video Encoder
• Manufacturer: NEC

3.2.3
3.2.4
interrupt mask, CINT does not become high even if the interrupt register becomes 1.
3.2.5
2AH
2BH
2CH
2DH
2EH
2FH
30H
Address
Address
Address
7 to 3
2
1
0
Host CPU set interrupt to internal CPU. Internal CPU clears this bit after interrupt operation.
The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H.
These registers are interrupt masks for next interrupt. Interrupt mask can be set bit by bit. When setting an
The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H.
It is set for 1 when the interrupt factor occurs.
The interrupt bit clears when host CPU writes to this register after the interrupt processing.
The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H.
Clear processing continues until interrupt registers is cleared.
It outputs DMA-RDY or DMA-DONE every 128-byte transfer. DMA-DONE is output when the transfer ends.
Bit
Internal CPU interrupt register
Interrupt mask register
Download interrupt register
Bit7
Bit7
Bit7
DMA-ERR
DMA-RDY
DMA-DONE
Field
Bit6
Bit6
Bit6
Reserved (set 0)
Data transfer error
0: Normal, 1: Error
Data transfer prepared
0: Normal, 1: Transfer
Data transfer ended
0: Normal, 1: Transfer ended
Bit5
Bit5
Bit5
Defined by firmware
Defined by firmware
Defined by firmware
Defined by firmware
Bit4
Bit4
Bit4
Data Sheet S15082EJ4V0DS
Bit3
Bit3
Bit3
Function
DMA-ERR
DMA-ERR DMA-RDY DMA-DON
Bit2
Bit2
Bit2
-M
DMA-RDY
Bit1
Bit1
Bit1
-M
DMA-DON
iCPU-INT
Bit0
Bit0
E-M
Bit0
E
µ
0
0
0
Initial value
PD61051, 61052
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Int. to internal CPU
Interrupt mask0
Interrupt mask1
Interrupt mask2
Interrupt mask3
Interrupt mask4
Interrupt0
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