AX88772 ASIX [ASIX Electronics Corporation], AX88772 Datasheet - Page 6

• Manufacturer Part Number: AX88772
• Description: USB to 10/100 Fast Ethernet/HomePNA Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

2.0 Signal Description
The following abbreviations apply to the following pin description table.
I2
I3
I5
O2
O3
O5
B
DP
DM
DPRS
DMRS
VBUS
XIN12M
XOUT12M
RREF
RPU
MDC
MDIO
MDINT
RX_CLK
RXD [3:0]
RX_DV
RX_ER
COL
Pin Name
Input, 2.5V with 3.3V tolerant
Input, 3.3V
Input, 3.3V with 5V tolerant
Output, 2.5V with 3.3V tolerant
Output, 3.3V
Output, 3.3V with 5V tolerant
Bi-directional I/O
I5/PD/S
B2/PU
I2/PU
Type
O3
O2
I3
I2
I2
I2
I2
I2
B
B
B
B
I
I
110, 109,
108, 107
Pin No
121
120
117
104
105
106
116
32
31
35
10
26
27
34
36
30
USB to 10/100 Fast Ethernet/HomePNA Controller
Table 1: Pinout Description
Station Management Interface
USB 2.0 data positive pin.
USB 2.0 data negative pin.
(+/-1%) serial resistor.
USB 1.1 data negative pin. Please connect to DM through a 39ohm
(+/-1%) serial resistor.
VBUS pin input. Please connect to USB bus power.
12Mhz crystal or oscillator clock input. This clock is needed for USB
PHY transceiver to operate.
12Mhz crystal or oscillator clock output.
12.1Kohm (+/-1%) resistor.
For USB PHY’s internal biasing. Please connect to AVDD3 (3.3V)
through a 1.5Kohm (+/-5%) resistor.
Station Management Data Clock output. The timing reference for
MDIO. All data transfers on MDIO are synchronized to the rising edge
of this clock. The frequency of MDC is 1.5MHz.
Station Management Data Input/Output. Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII spec.
Station Management Interrupt input.
USB 1.1 data positive pin. Please connect to DP through a 39ohm
For USB PHY’s internal biasing. Please connect to AGND through a
Receive Clock. RX_CLK is received from PHY to provide timing
reference for the transfer of RXD [7:0], RX_DV, and RX_ER signals
on receive direction of MII interface.
Receive Data. RXD [3:0] is driven synchronously with respect to
RX_CLK by PHY.
Receive Data Valid. RX_DV is driven synchronously with respect to
RX_CLK by PHY. It is asserted high when valid data is present on
RXD [3:0].
Receive Error. RX_ER is driven synchronously with respect to
RX_CLK by PHY. It is asserted high for one or more RX_CLK
periods to indicate to the MAC that an error has detected.
Collision Detected. COL is driven high by PHY when the collision is
detected.
USB Interface
MII Interface
6
B2
B5
PU
PD
P
S
Bi-directional I/O, 2.5V with 3.3V tolerant
Bi-directional I/O, 3.3V with 5V tolerant
Internal Pull Up (75K)
Internal Pull Down (75K)
Power Pin
Schmitt Trigger
Pin Description
ASIX ELECTRONICS CORPORATION
AX88772