S9S12GN16F0CFT Freescale Semiconductor, S9S12GN16F0CFT Datasheet - Page 147

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S9S12GN16F0CFT

Manufacturer Part Number
S9S12GN16F0CFT
Description
16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12GN16F0CFT

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
16 KB
Data Ram Size
1024 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
The operating mode out of reset is determined by the state of the MODC signal during reset (see
Table
mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge
of RESET.
1.10.1.1
This mode is intended for normal device operation. The opcode from the on-chip memory is being
executed after reset (requires the reset vector to be programmed correctly). The processor program is
executed from internal memory.
1.10.1.2
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin.
1.10.2
The MC9S12G has two static low-power modes Pseudo Stop and Stop Mode. For a detailed description
refer to S12CPMU section.
1.11
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to
“Security
1.12
Consult the S12 CPU manual and the S12SINT section for information on exception processing.
1.12.1
Table 1-34. lists all Reset sources and the vector locations. Resets are explained in detail in the
“S12 Clock, Reset and Power Management Unit
Freescale Semiconductor
1-33). The MODC bit in the MODE register shows the current operating mode and provides limited
Security
Resets and Interrupts
(S12XS9SECV2)”,
Low Power Operation
Resets
Normal Single-Chip Mode
Special Single-Chip Mode
Section 7.4.1,
MC9S12G Family Reference Manual, Rev.1.23
Normal single chip
Special single chip
Table 1-33. Chip Modes
Chip Modes
“Security”, and
(S12CPMU)”.
Section 29.5,
MODC
1
0
“Security”.
Device Overview MC9S12G-Family
Chapter 9,
Chapter 10,
149

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