S9S12GN16F0CFT Freescale Semiconductor, S9S12GN16F0CFT Datasheet - Page 395

• Manufacturer Part Number: S9S12GN16F0CFT
• Description: 16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN16F0CFT

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 1024 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT

10.3.2.18 S12CPMU IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML)
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register). Else write has no effect
Freescale Semiconductor
IRCTRIM[9:0]
TCTRIM[4:0]
0x02F8
0x02F9
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency f
After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to
provide trimmed Internal Reference Frequency f
Reset
Reset
15-11
Field
9-0
W
W
R
R
IRC1M temperature coefficient Trim Bits
Trim bits for the Temperature Coefficient (TC) of the IRC1M frequency.
Figure 10-26
temperature.
Figure 10-26
TCTRIM[4:0]=0b00000 or 0b10000).
IRC1M Frequency Trim Bits — Trim bits for Internal Reference Clock
After System Reset the factory programmed trim value is automatically loaded into these registers, resulting in a
Internal Reference Frequency f
The frequency trimming consists of two different trimming methods:
A rough trimming controlled by bits IRCTRIM[9:6] can be done with frequency leaps of about 6% in average.
A fine trimming controlled by the bits IRCTRIM[5:0] can be done with frequency leaps of about 0.3% (this
trimming determines the precision of the frequency setting of 0.15%, i.e. 0.3% is the distance between two
trimming values).
Figure 10-25
15
F
F
7
Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC
status bits.
Figure 10-23. S12CPMU IRC1M Trim High Register (CPMUIRCTRIMH)
Figure 10-24. S12CPMU IRC1M Trim Low Register (CPMUIRCTRIML)
shows the influence of the bits TCTRIM4:0] on the relationship between frequency and
shows an approximate TC variation, relative to the nominal TC of the IRC1M (i.e. for
shows the relationship between the trim bits and the resulting IRC1M frequency.
14
F
F
6
Table 10-22. CPMUIRCTRIMH/L Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
TCTRIM[4:0]
13
F
F
5
IRC1M_TRIM
IRC1M_TRIM
IRC1M_TRIM
. See device electrical characteristics for value of f
NOTE
12
F
F
4
.
.
IRCTRIM[7:0]
Description
S12 Clock, Reset and Power Management Unit (S12CPMU)
11
F
0
3
10
0
0
F
2
F
F
9
1
IRCTRIM[9:8]
IRC1M_TRIM
F
F
8
0
.
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