S9S12P128J0MFTR Freescale Semiconductor, S9S12P128J0MFTR Datasheet - Page 148

• Manufacturer Part Number: S9S12P128J0MFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P128J0MFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

Device Overview MC9S12G-Family
1.12.2
Table 1-35
Chapter 6, “Interrupt Module
the vectors.
150
Vector base + $EC
Vector base + $DA
Vector base + $F8
Vector base + $E2
Vector base+ $DC
Vector base + $D8
Vector base + $D4
Vector base+ $EE
Vector base+ $EA
Vector base+ $DE
Vector base+ $F6
Vector base+ $F4
Vector base+ $F2
Vector base+ $F0
Vector base+ $E8
Vector base+ $E6
Vector base+ $E4
Vector base+ $E0
Vector base+ $D6
Vector Address
Vector Address
lists all interrupt sources and vectors in the default order of priority. The interrupt module (see
Interrupt Vectors
$FFFC
$FFFE
$FFFE
$FFFE
$FFFE
$FFFA
1
TIM Pulse accumulator input edge
TIM Pulse accumulator A overflow
Unimplemented instruction trap
RTI time-out interrupt
TIM timer channel 0
TIM timer channel 1
TIM timer channel 2
TIM timer channel 3
TIM timer channel 4
TIM timer channel 5
TIM timer channel 6
TIM timer channel 7
Table 1-35. Interrupt Vector Locations (Sheet 1 of 2)
TIM timer overflow
Interrupt Source
Table 1-34. Reset Sources and Vector Locations
(S12SINTV1)”) provides an interrupt vector base register (IVBR) to relocate
XIRQ
SPI0
SCI0
SCI1
MC9S12G Family Reference Manual,
SWI
IRQ
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
COP watchdog reset
External pin RESET
Clock monitor reset
Reset Source
2
3
Mask
None
None
CCR
X Bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
SPI0CR1 (SPIE, SPTIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
CPMUINT (RTIE)
Mask
None
None
None
None
None
None
IRQCR (IRQEN)
CCR
PACTL (PAOVI)
Local Enable
TSCR2 (TOI)
PACTL (PAI)
Rev.1.23
SCI0CR2
SCI1CR2
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
None
None
None
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
Local Enable
None
None
None
None
Freescale Semiconductor
from STOP
Wake up
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
10.6 Interrupts
-
-
from WAIT
Wakeup
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-