S9S12P128J0MFTR Freescale Semiconductor, S9S12P128J0MFTR Datasheet - Page 619

• Manufacturer Part Number: S9S12P128J0MFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P128J0MFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

The MSCAN then schedules the message for transmission and signals the successful transmission of the
buffer by setting the associated TXE flag. A transmit interrupt (see
is generated
If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration,
the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this
purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs
this field when the message is set up. The local priority reflects the priority of this particular message
relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field
is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN
arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error.
When a high priority message is scheduled by the application software, it may become necessary to abort
a lower priority message in one of the three transmit buffers. Because messages that are already in
transmission cannot be aborted, the user must request the abort by setting the corresponding abort request
bit (ABTRQ) (see
(CANTARQ)”.) The MSCAN then grants the request, if possible, by:
18.4.2.3
The received messages are stored in a five stage input FIFO. The five message buffers are alternately
mapped into a single memory area (see
exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the
CPU (see
applicable for the receive process.
All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or
extended), the data contents, and a time stamp, if enabled (see
Message
The receiver full flag (RXF) (see
signals the status of the foreground receive buffer. When the buffer contains a correctly received message
with a matching identifier, this flag is set.
On reception, each message is checked to see whether it passes the filter (see
Acceptance
valid message, the MSCAN shifts the content of RxBG into the receiver FIFO, sets the RXF flag, and
generates a receive interrupt
handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the
interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS
field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid
1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also.
2. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.
Freescale Semiconductor
1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register.
2. Setting the associated TXE flag to release the buffer.
3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the
setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).
Storage”).
Figure
1
Filter”) and simultaneously is written into the active RxBG. After successful reception of a
Receive Structures
when TXEx is set and can be used to drive the application software to re-load the buffer.
18-39). This scheme simplifies the handler software because only one address area is
Section 18.3.2.9, “MSCAN Transmitter Message Abort Request Register
2
(see
MC9S12G Family Reference Manual, Rev.1.23
Section 18.3.2.5, “MSCAN Receiver Flag Register
Section 18.4.7.3, “Receive
Figure
18-39). The background receive buffer (RxBG) is
Freescale’s Scalable Controller Area Network (S12MSCANV3)
Interrupt”) to the CPU. The user’s receive
Section 18.3.3, “Programmer’s Model of
Section 18.4.7.2, “Transmit
Section 18.4.3, “Identifier
(CANRFLG)”)
Interrupt”)
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