S9S12P128J0MFTR Freescale Semiconductor, S9S12P128J0MFTR Datasheet - Page 749

• Manufacturer Part Number: S9S12P128J0MFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P128J0MFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

Chapter 23
Timer Module (TIM16B8CV3)
23.1
The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible
programmable prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from microseconds to many seconds.
This timer could contain up to 8 input capture/output compare channels with one pulse accumulator
available only on channel 7. The input capture function is used to detect a selected transition edge and
record the time. The output compare function is used for generating output signals or for timer software
delays. The 16-bit pulse accumulator is used to operate as a simple event counter or a gated time
accumulator. The pulse accumulator shares timer channel 7 when the channel is available and when in
event mode.
A full access for the counter registers or the input capture/output compare registers should take place in
one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the
same result as accessing them in one word.
23.1.1
The TIM16B8CV3 includes these distinctive features:
Freescale Semiconductor
V03.00
V03.01
V03.02
V03.03
•
Up to 8 channels available. (refer to device specification for exact number)
Introduction
Features
Aug. 26, 2009
Jan. 28, 2009
Apri,12,2010
Jan,14,2013
23.3.2.2/23-758,
23.3.2.3/23-758,
23.3.2.4/23-759,
Figure 23-4./23-
23.3.2.15/23-76
23.3.2.8/23-762
23.3.2.11/23-76
23.1.2/23-752
23.4.3/23-774
23.4.3/23-774
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MC9S12G Family Reference Manual, Rev.1.23
8
5
Initial version
- Correct typo: TSCR ->TSCR1;
- Correct typo: ECTxxx->TIMxxx
- Correct reference:
- Add description, “a counter overflow when TTOV[7] is set”, to be the
condition of channel 7 override event.
- Phrase the description of OC7M to make it more explicit
-Add
-update TCRE bit description
-add
-single source generate different channel guide
Figure 23-31
Table 23-10
Table 23-1.
Figure 23-25
->
Figure 23-30
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