S9S12P128J0MFTR Freescale Semiconductor, S9S12P128J0MFTR Datasheet - Page 607

• Manufacturer Part Number: S9S12P128J0MFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P128J0MFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

18.3.3
The following section details the organization of the receive and transmit message buffers and the
associated control registers.
To simplify the programmer interface, the receive and transmit message buffers have the same outline.
Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last
two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an
internal timer after successful transmission or reception of a message. This feature is only available for
transmit and receiver buffers, if the TIME bit is set (see
(CANCTL0)”).
The time stamp register is written by the MSCAN. The CPU can only read these registers.
Figure 18-24
identifiers. The mapping of standard identifiers into the IDR registers is shown in
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
1. Exception: The transmit buffer priority registers are 0 out of reset.
Freescale Semiconductor
1
Not applicable for receive buffers
Address
0x00XA
0x00XB
0x00XC
0x00XD
0x00XE
0x00X0
0x00X1
0x00X2
0x00X3
0x00X4
0x00X5
0x00X6
0x00X7
0x00X8
0x00X9
0x00XF
Offset
Programmer’s Model of Message Storage
shows the common 13-byte data structure of receive and transmit buffers for extended
Identifier Register 0
Identifier Register 1
Identifier Register 2
Identifier Register 3
Data Segment Register 0
Data Segment Register 1
Data Segment Register 2
Data Segment Register 3
Data Segment Register 4
Data Segment Register 5
Data Segment Register 6
Data Segment Register 7
Data Length Register
Transmit Buffer Priority Register
Time Stamp Register (High Byte)
Time Stamp Register (Low Byte)
Table 18-26. Message Buffer Organization
MC9S12G Family Reference Manual, Rev.1.23
1
Register
Section 18.3.2.1, “MSCAN Control Register 0
Freescale’s Scalable Controller Area Network (S12MSCANV3)
Figure
Access
18-25.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
1
609
.