S9S12P128J0MFTR Freescale Semiconductor, S9S12P128J0MFTR Datasheet - Page 324

• Manufacturer Part Number: S9S12P128J0MFTR
• Description: 16-bit Microcontrollers - MCU 16 BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12P128J0MFTR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8192 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: QFN-48
• Mounting Style: SMD/SMT

S12S Debug Module (S12SDBGV2)
The priorities described in
final state has priority followed by the match on the lower channel number (0,1,2).
8.3.2.7.4
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further comparator matches on the same channel in the same session have no affect on that flag.
8.3.2.8
Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module
register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data
bus compare registers, two data bus mask registers and a control register). Comparator B consists of four
326
Address: 0x0027
SC[3:0]
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
W
R
Comparator Register Descriptions
0
0
7
Debug Match Flag Register (DBGMFR)
= Unimplemented or Reserved
0
0
6
Table 8-20. State3 — Sequencer Next State Selection
Table 8-36
Figure 8-12. Debug Match Flag Register (DBGMFR)
Either Match1 or Match2 to State1....... Match0 to Final State
Either Match1 or Match2 to Final State....... Match0 to State1
MC9S12G Family Reference Manual, Rev.1.23
Description (Unspecified matches have no effect)
dictate that in the case of simultaneous matches, a match leading to
0
0
5
Match2 to State2........ Match0 to Final State
Match2 to State2........ Match1 to Final State
Match0 to Final State....... Match1 to State1
Match1 to Final State....... Match2 to State1
Match0 to State2....... Match2 to Final State
Match1 to Final State
Match0 to Final State
0
0
4
Match1 to State2
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
3
MC2
0
2
Freescale Semiconductor
MC1
0
1
MC0
0
0