AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 359
AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
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31. Universal Synchronous Asynchronous Receiver Transceiver (USART)
31.1
Overview
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal syn-
chronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop
bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error
detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates
communications with slow remote devices. Multidrop communications are also supported through address bit han-
dling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1
smart card slots, and infrared transceivers and connection to modem ports. The hardware handshaking feature
enables an out-of-band flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the trans-
mitter and from the receiver. The PDC provides chained buffer management without any intervention of the
processor.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
359
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