AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 622

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.6.11.5
40.6.12
40.6.12.1
40.6.12.2
40.6.12.3
40.6.12.4
40.6.12.5
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR.
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is cor-
rupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if
this occurs.
The user must be sure that received data is read before transmitting any new data.
When Hardware Handshaking is used and if CTS goes low near the end of the starting bit, a character can be lost.
CTS must not go low during a time slot occurring between 2 Master Clock periods before the starting bit and 16
Master Clock periods after the rising edge of the starting bit.
If CTS switches from 0 to 1 during the TX of a character and if the holding register (US_THR) is not empty, the con-
tent of US_THR will also be transmitted.
Don't use the PDC in transmit mode and do not fill US_THR before TXEMPTY is set at 1.
The XOFF character is sent only when the receive buffer is detected full. While the XOFF is being sent, the remote
transmitter is still transmitting. As only one Holding register is available in the receiver, characters will be lost in
reception. This makes the software handshaking functionality ineffective.
None.
In receiver mode, when there are two consecutive characters (without timeguard in between), RXBRK is not taken
into account. As a result, the RXBRK flag is not enabled correctly and the frame error flag is set.
Constraints on the transmitter device connected to the SAM7S USART receiver side:
The transmitter may use the timeguard feature or send two STOP conditions. Only one STOP condition is taken
into account by the receiver state machine. After this STOP condition, as there is no valid data, the receiver state
machine will go in idle mode and enable the RXBRK flag.
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Add an inverter.
Universal Synchronous Asynchronous Receiver Transmitter (USART)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
TWI: Possible Receive Holding Register Corruption
USART: CTS in Hardware Handshaking
USART: Hardware Handshaking – Two Characters Sent
USART: XOFF Character Bad Behavior
USART: RXBRK Flag Error in Asynchronous Mode
USART: DCD is active High instead of Low
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
622