AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 638

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.8.6.4
40.8.6.5
40.8.6.6
40.8.6.7
40.8.6.8
SPCK pin can toggle out before the first transfer in Master Mode.
Problem Fix/Workaround
In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers.
In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip select 0, the output
spi_size sampled by the PDC will depend on the field, BITS (Bits per Transfer) of SPI_CSR0 register, whatever the
selected Chip select is. For example, if SPI_CSR0 is configured for a 10-bit transfer whereas SPI_CSR1 is config-
ured for an 8-bit transfer, when a transfer is performed in Fixed mode through the PDC, on Chip select 1, the
transfer will be considered as a HalfWord transfer.
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y as different from 0), the BITS field of the
SPI_CSR0 must be configured in 8 bits, in the same way as the BITS field of the CSRy Register.
When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency) and when the BITS
field of the SPI_CSR register (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15),
an additional pulse will be generated on output SPCK.
Everything is OK if the BITS field equals 8,10,12,14 or 16 and Baudrate = 1.
None.
The SPI disable is not possible in slave mode.
Read first the received data, then perform the software reset.
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and
the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock
• Transmitting with the slowest chip select and then with the fastest one, then an additional
frequency equals the system clock frequency) and the other transfers set with SCBR are not equal to 1
on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SPI: SPCK Behavior in Master Mode
SPI: Chip Select and Fixed Mode
SPI: Baudrate Set to 1
SPI: Disable In Slave Mode
SPI: Bad Serial Clock Generation on 2nd Chip Select
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
pulse is generated
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