AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 734

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.23 SAM7S32 Errata - Revision B Parts
40.23.1
40.23.1.1
40.23.1.2
40.23.1.3
40.23.1.4
40.23.1.5
40.23.1.6
Refer to
Note: AT91SAM7S32 Revision B chip ID is 0x2708 0341.
The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any
ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag.
None
When reading LCDR at the same instant as an end of conversion, with DRDY already active, DRDY is kept active
regardless of the enable status of the current channel. This sets DRDY, whereas new data is not stored.
None
Reading CDR for channel “y” at the same instant as an end of conversion on channel “x” with EOC[x] already
active, leads to skipping to set the DRDY flag if channel “x” is enabled.
Use of DRDY functionality with access to CDR registers should be avoided.
DRDY does not rise when disabling channel “y” at the same time as an end of “x” channel conversion, although
data is stored into CDRx and LCDR.
None.
Read of the Status Register at the same instant as an end of conversion leads to skipping the update of the
GOVRE (general overrun) flag. GOVRE is neither reset nor set.
For example, if reading the status while an end of conversion is occurring and:
None
When reading CDRy (Channel Data Register y) at the same instant as an end of conversion on channel “x” with the
following conditions:
1. GOVRE is active but DRDY is inactive, does not correspond to a new general overrun condition but the
2. GOVRE is inactive but DRDY is active, does correspond to a new general overrun condition but the
• EOC[x] already active,
• DRDY already active,
Analog-to-Digital Converter (ADC)
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
ADC: DRDY Bit Cleared
ADC: DRDY not Cleared on Disable
ADC: DRDY Possibly Skipped due to CDR Read
ADC: Possible Skip on DRDY when Disabling a Channel
ADC: GOVRE Bit is not Updated
ADC: GOVRE Bit is not Set when Reading CDR
GOVRE flag is not reset.
GOVRE flag is not set.
Section 40.1 “Marking” on page
595.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
734