AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 664

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.12.11.5
40.12.12 Voltage Regulator
40.12.12.1
40.12.12.2
40.12.13 Watchdog Timer (WDT)
40.12.13.1
40.12.13.2
Constraints on the transmitter device connected to the SAM7S USART receiver side:
The transmitter may use the timeguard feature or send two STOP conditions. Only one STOP condition is taken
into account by the receiver state machine. After this STOP condition, as there is no valid data, the receiver state
machine will go in idle mode and enable the RXBRK flag.
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Add an inverter.
Current consumption in Deep Mode is maximum 60 µA instead of 25 µA.
Due to current rejection from VDDIN to VDDCORE, the current consumption in Deep Mode cannot be guaranteed.
Instead, 60 µA is guaranteed whatever the condition.
None.
Maximum load is 50 mA at 85 °C (instead of 100 mA).
Maximum load is 100 mA at 70°C.
None.
Under certain rare circumstances, if the Watchdog Timer is used with the Watchdog Reset enabled (WDRSTEN
set at 1), the Watchdog Timer may lock the device in a reset state when the user restarts the watchdog
(WDDRSTT). The only way to recover from this state is a power-on reset. The issue depends on the values of
WDD and WDV in the WDT_MR register.
Two workarounds are possible.
Under certain rare circumstances, if the Watchdog Timer is used with the Watchdog Fault Interrupt enabled
(WDFIEN set at 1), the Watchdog Timer may trigger the interrupt (wdt_fault) erroneously. The Watchdog Timer
Status Register may be wrong also (WDERR and WDUNF). The issue depends on the values of WDD and WDV in
the WDT_MR register.
1. Either do not use the Watchdog Timer with the Watchdog Reset enabled (WDRSTEN set at 1),
2. or set WDD to 0xFFF and in addition use only one of the following values for WDV: 0xFFF, 0xDFF, 0xBFF,
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
USART: DCD is active High instead of Low
Voltage Regulator: Current Consumption in Deep Mode
Voltage Regulator: Load Versus Temperature
WDT: The Watchdog Timer May Lock the Device in a Reset State
WDT: The Watchdog Timer Status Register and Interrupt
0x9FF, 0x7FF, 0x77F, 0x6FF, 0x67F, 0x5FF, 0x57F, 0x4FF, 0x47F, 0x3FF, 0x37F, 0x2FF, 0x27F, 0x1FF,
0x1BF, 0x17F, 0x13F, 0x0FF, 0x0DF, 0x0BF, 0x09F, 0x07F, 0x06F, 0x05F, 0x04F, 0x03F, 0x037, 0x02f,
0x027, 0x01F, 0x01B, 0x017, 0x013 and 0x00F.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
664