AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 512

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Figure 35-10. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints
When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions:
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0.
3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data
4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in
5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s
6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s mem-
7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing
8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0.
9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1
10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s mem-
11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the
12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0.
OUT packet. It is accepted by the device and copied to FIFO Bank 1.
the endpoint’s UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set.
UDP_ CSRx register.
ory. Data received is made available by reading the endpoint’s UDP_ FDRx register.
RX_DATA_BK0 in the endpoint’s UDP_ CSRx register.
set in the endpoint’s UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is
set.
ory. Data received is available by reading the endpoint’s UDP_ FDRx register.
endpoint’s UDP_ CSRx register.
1 st Data Payload
2 nd Data Payload
3 rd Data Payload
Microcontroller
Write and Read at the Same Time
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Write
USB Device
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Read
USB Bus
SAM7S Series [DATASHEET]
2 nd Data Payload
3 rd Data Payload
1 st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
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