ATAES132-TH-EQ Atmel, ATAES132-TH-EQ Datasheet - Page 123

• Manufacturer Part Number: ATAES132-TH-EQ
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-TH-EQ

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Interface Type: SPI
• Factory Pack Quantity: 2300

J.1.5.
J.1.6.
J.1.7.
J.1.8.
J.1.9.
I
A high-to-low transition of SDA with SCK high is an I
device address for any instruction. I
allowed to generate an I
The slave will reset its serial interface immediately when an I
be followed immediately with an I
I
A low-to-high transition of SDA with SCK high is an I
Host is driving the bus – slaves are not allowed to generate an I
condition.
Figure J-1.
I
All addresses and data words are serially transmitted to and from the ATAES132 in 8-bit words. The receiving I
sends a zero (ACK) during the ninth clock cycle to acknowledge receipt of each byte.
An I
to accept a new instruction. See Section J.3.8 for a discussion of ACK polling.
I
When the receiving I
SDA remains high due to the external pull-up resistor. This generates a NO ACK (NAK) signal to the device sending the byte.
Data Format
All instructions and data on the I
by the receiving device. The MSB is the first bit of each byte transmitted and received.
SDA
SCL
2
2
2
2
C START Condition
C STOP Condition
C ACK
C NAK
2
C Host can use acknowledge polling to monitor the progress of an EEPROM write and to determine if the slave is ready
S
T
I
2
A
C START condition and I
R
T
2
C device fails to send a zero during the ninth clock cycle to acknowledge that it has received a byte, then
2
C START condition.
2
C bus must be formatted as eight bit bytes, followed by a ninth bit (ACK or NAK) generated
2
C STOP condition. Figure J-1 illustrates an I
2
C START conditions are only generated when the Host is driving the bus – slaves are not
2
C STOP condition definitions
2
2
C START condition. An I
C STOP condition. I
2
S
C START condition is received. An I
T
2
O
C STOP condition. Figure J-1 illustrates an I
P
Atmel ATAES132 Preliminary Datasheet
2
C STOP conditions are only generated when the
2
2
C START condition must precede the I
C START condition.
2
C START condition cannot
8760A−CRYPTO−5/11
2
C STOP
2
C device
2
C
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