ATAES132-TH-EQ Atmel, ATAES132-TH-EQ Datasheet - Page 153

• Manufacturer Part Number: ATAES132-TH-EQ
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-TH-EQ

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Interface Type: SPI
• Factory Pack Quantity: 2300

Appendix P. Serial Memory Backward Compatibility
P.1.
P.1.1. Package Pins
P.1.2. I
P.1.3. Write Protect
P.1.4. Page Write Operations
The ATAES132 Secure Serial EEPROM architecture was developed to allow security to be retrofitted into systems using
standard Atmel Serial EEPROM. The ATAES132 package pinouts, the interface protocol, and the command set are all
compatible with standard I
This section describes the differences which must be considered when the ATAES132 is inserted into systems using I
SPI Serial EEPROM.
I
This section describes differences between the Atmel AT24C32C standard Atmel 32K bit I
ATAES132 Secure Serial EEPROM configured for I
On AT24C32C pins 1, 2, and 3 are used to set I
(WP) input.
On ATAES132 pins 1, 2, 3, and 7 are not used in I
state of these four pins has no impact on the functionality of the ATAES132 in the I
for the pin descriptions.
The AT24C32C I
maximum of eight AT24C32C devices are permitted on the I
On the ATAES132, the I
ATAES132 I
The AT24C32C write protect (WP) input pin inhibits all EEPROM write operations when the WP pin is high. If WP is low, then
EEPROM write operations are allowed.
On the ATAES132, the user memory write permissions are controlled by the ZoneConfig Registers (see Section E.2.22). The
user memory is divided into 16 user zones which are independently controlled by 16 ZoneConfig Registers – different write
permissions can be assigned to different sections of the memory. By default all user memory has open write access.
If the host attempts to write data across the physical (32 byte) EEPROM page boundary, the AT24C32C wraps to the
beginning of the EEPROM page where the page write operation begins and performs the EEPROM write after receiving a
STOP condition. If the host attempts to write more than 32 bytes in a page write operation, then the AT24C32C wraps the
data at the page boundary and performs the EEPROM write after receiving a STOP condition. Partial page writes are
supported by the AT24C32C.
The ATAES132 does not allow write operations to cross physical (32 byte) EEPROM page boundaries (see Section B.2), and
does not allow a write operation if more than 32 data bytes are received from the host. In both cases the EEPROM contents
remain unchanged, the data is discarded, and an error bit is set in the STATUS register (see Section J.3.3). Partial page
writes are supported by the ATAES132.
2
2
C Device Address
C Serial EEPROM Compatibility
2
C device address can be any set to any value, allowing up to 127 devices on the I
2
C device address is 1010A
2
C device address is determined by the contents of the I
2
C and SPI EEPROM, but are not identical.
2
A
1
2
A
C device address bits A
0
2
b, with A
C communication mode. These pins should be tied to V
2
C communication mode.
0
, A
2
C interface.
1
, and A
2
determined by the state of pins one, two, and three. A
0
Atmel ATAES132 Preliminary Datasheet
, A
1
, and A
2
CAddr register (see Section J.1.3). The
2
C communication mode. See Section J.2
2
. AT24C32C pin 7 is the write protect
2
C Serial EEPROM and the
2
C interface.
8760A−CRYPTO−5/11
CC
or V
SS
. The
2
C or
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