ATAES132-TH-EQ Atmel, ATAES132-TH-EQ Datasheet - Page 95

• Manufacturer Part Number: ATAES132-TH-EQ
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-TH-EQ

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Interface Type: SPI
• Factory Pack Quantity: 2300

Appendix G. Understanding the STATUS Register
G.1.
The device status register is used for handshaking between the host microcontroller and the ATAES132. The host
microcontroller is expected to read the STATUS register before sending a command or reading a response.
Device Status Register (STATUS) Definition
Address 0xFFF0 contains the read-only device status register which indicates the current status of the ATAES132 device. The
SPI read status register command can be used to read the STATUS register as described in Section K.3.6.
This register can also be read with the standard I
increment the memory read address, so a host microcontroller can easily monitor the ATAES132 device status by repeatedly
reading the STATUS register.
Table G-22. Device status register definition
Table G-23. Device status register bit definitions
Notes:
The device status register can always be read when the ATAES132 is configured for SPI interface mode, even when the
ATAES132 is processing a command or writing the EEPROM. When the ATAES132 is configured for I
random read command can only be used to read the STATUS register when the device address is ACKed.
If the ATAES132 is in the sleep or standby power state, reading the STATUS register forces the ATAES132 to wakeup – the
STATUS register is 0xFF until the wakeup process is complete.
Bit
Bit 0 (WIP)
Bit 1 (WEN)
Bit 2 (WAKEb)
Bit 3 (Reserved)
Bit 4 (CRCE)
Bit 5 (Reserved)
Bit 6 (RRDY)
Bit 7 (EERR)
EERR
Bit 7
1.
2. STATUS register bits 0 - 7 are "1b"s during wakeup. During the first phase of wakeup (t
When the SPI RDSR command is used to read the STATUS register during an EEPROM write or during
execution of any ATAES132 command, then status bits 0 - 7 are "1b"s (See Section K.3.6). When the STATUS
register is read from address 0xFFF0 under the same circumstances, the reserved bits will read as 0b.
tri-stated and any attempt to read it will be system-dependent. See Appendix L for additional information.
RRDY
Bit 6
Definition
“0b” indicates the device is ready, waiting for a command
“1b” indicates a write cycle or a cryptographic operation is in progress
"0b" indicates the device is not SPI write enabled, or is in I
“1b” indicates the device is SPI write enabled
"0b" indicates the device is not in the Sleep or Standby power state
“1b” indicates the device is in the Sleep or Standby power state
Always "0b". This bit is reserved for future use.
"0b" indicates the most recent command block contained a correct checksum (CRC)
“1b” indicates the most recent command block contained an error
Always "0b". This bit is reserved for future use.
"0b" indicates the response memory buffer is empty
“1b” indicates the response memory buffer is ready to read
"0b" indicates the most recent command did not generate an error during execution
“1b” indicates the most recent command generated an execution error
Reserved
Bit 5
2
(1)(2)
C or SPI read memory commands. Reading the STATUS register does not
CRCE
Bit 4
Reserved
Bit 3
Atmel ATAES132 Preliminary Datasheet
(1)
(1)
2
WAKEb
C interface mode
Bit 2
PU.STATUS
WEN
Bit 1
8760A−CRYPTO−5/11
2
C interface mode, the
), the SO pin is
Bit 0
WIP
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