ATAES132-TH-EQ Atmel, ATAES132-TH-EQ Datasheet - Page 127

• Manufacturer Part Number: ATAES132-TH-EQ
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-TH-EQ

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Interface Type: SPI
• Factory Pack Quantity: 2300

J.3.6.
J.3.7.
Figure J-5.
Sequential Read (SREAD)
Sequential reads are initiated by either a current address read or a random read. After the host microcontroller receives a data
byte, it responds with an I
byte address and serially clock out sequential data bytes. The sequential read operation is terminated when the
microcontroller responds with an I
When any error occurs, the EERR bit of the STATUS register is set to 1b to indicate an error. If the command is processed
without error the EERR bit is set to 0b.
Note:
Figure J-6.
Software Reset (SRESET)
After an interruption in protocol, power loss or system reset, the ATAES132 in I
following these steps:
The device is ready for next communication after these steps have been completed. The internal data address is also reset to
0000h by this procedure.
SDA LINE
SDA LINE
•
•
•
Send a START condition
Clock 9 cycles
Send another START condition followed by STOP condition as shown below
ADDRESS
DEVICE
S
R
T
A
T
Random read
If an I
1b. Attempting to read protected memory will result in 0xFF data returned to the host for each protected byte
address.
Sequential read
M
S
B
ADDRESS
DEVICE
2
C read begins at an authorized address and continues into protected memory, the EERR bit will be set to
W
R
E
D
R
A
/
C
K
A
DUMMY WRITE
2
C ACK. As long as the EEPROM receives an acknowledge, it will continue to increment the data
S
B
L
W
W
R
R
T
E
/
I
DATA n
C
A
K
2
C NAK and a following STOP condition.
1st, 2nd WORD
ADDRESS n
A
C
K
DATA n + 1
C
A
K
S
A
R
T
T
ADDRESS
DEVICE
C
K
A
DATA n + 2
Atmel ATAES132 Preliminary Datasheet
R
E
A
D
A
C
K
2
C interface mode can be protocol reset by
DATA n
C
A
K
DATA n + 3
N
O
C
K
A
S
O
P
T
8760A−CRYPTO−5/11
N
O
C
K
A
S
O
P
T
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