ATAES132-TH-EQ Atmel, ATAES132-TH-EQ Datasheet - Page 124

• Manufacturer Part Number: ATAES132-TH-EQ
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-TH-EQ

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Interface Type: SPI
• Factory Pack Quantity: 2300

J.2.
J.2.1.
J.2.2.
J.2.3.
J.2.4.
J.2.5.
J.2.6.
J.2.7.
J.2.8.
Pin Descriptions
When the ATAES132 is configured in the I
described in this section.
Note:
In the I
functionality or active state power consumption of the ATAES132 when I
SO [Pin 2]
In the I
this configuration, the pin can be tied to V
consumption of the ATAES132 when I
If Auth signaling is enabled, then the SO pin functions as the AuthO signal output. In this configuration the AuthO signal is high
after a specified key is authenticated. The AuthO output is in the high impedance state when the device has not authenticated.
See Section J.5 for the Auth signaling specifications.
N.C. [Pin 3]
No connect pin. This package pin is not used and can be left open by the user. The state of this pin does not affect the
functionality or power consumption of the ATAES132.
V
Ground
SI / SDA [Pin 5]
Bidirectional serial sata I/O pin. In the I
open drain buffer and may be wire ORed with any number of other open drain or open collector devices. The SDA pin must
be pulled high with an external resistor for the I
Data on the SDA pin may change only during the SCK low time periods. Data changes during SCK high periods indicate a I
START or I
Section J.3; the host and client cannot simultaneously drive the SDA line.
SCK [Pin 6]
Serial Clock input pin. In the I
used to transfer data in to the ATAES132 on the rising edge of clock and to transfer data out on the falling edge of clock. The
ATAES132 never drives SCK because it is a standard-mode I
The SCK line is high when the bus is idle.
If the I
master uses an open drain or open collector output to drive SCK, then an external pull-up resistor is required.
N.C. [Pin 7]
No connect pin. This package pin is not used and can be left open by the user. The state of this pin does not affect the
functionality or power consumption of the ATAES132.
Vcc [Pin 8]
Supply voltage. Power cannot be removed from the ATAES132 when the I
permanently damaged if the requirements in Section 9.1 and Section 9.3 are exceeded.
SS
[Pin 1]
[Pin 4]
2
2
2
C master uses a normal totem pole output to drive SCK, then no pull-up resistor is required on the SCK line. If the I
C communication mode, this pin is not used and should be tied to V
C communication mode, this pin is not used in the default configuration. It is always in the high impedance state. In
The pin numbers listed here are the SOIC, TSSOP, and UDFN package pin numbers.
2
C STOP condition. Data transfer on the SDA line is half-duplex as described by the I
2
C communication mode, this pin is used as the serial interface clock (SCK). The SCK input is
2
2
C communication mode is selected.
C communication mode, this pin functions as the serial data I/O (SDA). This pin is an
CC
2
C interface communication mode, the package pins are assigned the functionality
or V
2
C bus to operate correctly.
SS
. The state of this pin does not affect the functionality or active state power
2
C slave device – slave device clock stretching is not supported.
2
Atmel ATAES132 Preliminary Datasheet
C communication mode is selected.
2
C interface is active. The device may be
CC
or V
SS
. The state of this pin does not affect the
2
C command definitions in
8760A−CRYPTO−5/11
2
124
C
2
C