ATAES132-TH-EQ Atmel, ATAES132-TH-EQ Datasheet - Page 58

• Manufacturer Part Number: ATAES132-TH-EQ
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-TH-EQ

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Interface Type: SPI
• Factory Pack Quantity: 2300

7.20.
Nonce Command
The nonce command generates and/or stores a 96 bit nonce in the SRAM nonce register for use by subsequent cryptographic
commands. It is not necessary to generate a new nonce before each cryptographic operation because the ATAES132
includes the MacCount in the MAC calculations (see Section I.1) to guarantee uniqueness.
There are two nonce command options:
If the LockConfig register is unlocked (0x55), then the random number generator is latched in the test mode and executing the
nonce command with mode bit 0 = 1b will generate non-random values. If the LockConfig register is locked (0x00) then the
RNG generates random numbers and the nonce command functions normally.
The nonce remains valid until one of the following events occurs:
If a cryptographic operation involves two ATAES132 devices and a synchronized nonce is required, then the nonce
synchronization procedure in Section 7.21.1 must be used. The nonce command cannot be used to generate a synchronized
random nonce.
Warning:
1.
2.
•
•
•
•
Inbound nonce
Random nonce
A MAC compare operation fails
The MacCount reaches the maximum count (See Section I.1)
The cryptographic state machine is reset due to: receipt of a reset command, power cycling (POR), or activation of
The execution of the nonce command resets the MacCount to zero (see Section I.1)
The InSeed value is written directly to the nonce register. No random number generation or cryptographic nonce
calculation is performed.
Note:
The InSeed value is cryptographically combined with the new output of the random number generator and stored in
the nonce register. The random number used for the nonce calculation is returned to the host in the response. See
Section I.31 for the nonce algorithm.
the initialization sequence due to WakeUp from the sleep power state (see Section G.2.2)
There is one random number generator (RNG) seed register in the EEPROM memory which is used by the
KeyCompute, KeyExport, nonce, and random commands. The RNG seed register is subject to the same
write endurance limitations as the other bytes in the EEPROM (see Section 9.2 for the EEPROM
specifications) – the application developer must not exceed the write endurance limit.
This option provides no defense against replay attacks or known plaintext attacks.
Atmel ATAES132 Preliminary Datasheet
8760A−CRYPTO−5/11
58