ATAES132-TH-EQ Atmel, ATAES132-TH-EQ Datasheet - Page 62

• Manufacturer Part Number: ATAES132-TH-EQ
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-TH-EQ

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Interface Type: SPI
• Factory Pack Quantity: 2300

7.22.
Random Command
The random command generates a random number using the internal high quality random number generator and the random
number generation procedure recommended by NIST in SP800-90 (see Appendix A). The random command returns the
generated random number to the host.
There are two random command options:
If the LockConfig register is unlocked (0x55), then the random number generator is latched in the test mode, and the random
command will always return 16 bytes of 0xA5. If the LockConfig register is locked (0x00), then the RNG generates random
numbers.
Warning:
Table 7-65. Input parameters
Note:
Opcode
Mode
Param1
Param2
Data
1.
2.
Random number generation:
Nonce synchronization:
If mode bit 2 is 0b, the 16 byte random number is only returned to the host, it is not stored internally. This option
does not affect the cryptographic state of the device.
If mode bit 2 is 1b, then the first 12 bytes of the random number are stored in the nonce register for later use by the
NonceCompute command. The 16 byte random number is returned to the host. The nonce status flags are changed
to NonceValid = YesNonce, NonceRandom = Fixed, and NonceCompute = Yes. See Section 7.21 for the
NonceCompute command and the nonce synchronization procedure.
1.
There is one random number generator (RNG) seed register in the EEPROM memory, which is used by the
KeyCompute, KeyExport, nonce, and random commands. The RNG seed register is subject to the same
write endurance limitations as the other bytes in the EEPROM (see Section 9.2 for the EEPROM
specifications) – the application developer must not exceed the write endurance limit.
The RNG seed register in the EEPROM will be updated automatically if mode bit 1 = 0b unless the seed register
was previously updated after the most recent power on reset, wake from the sleep state, reset command, or
tamper event. Updating the RNG seed register increases the randomness of the random command output,
however, the EEPROM write endurance specification must be respected.
Name
Random
Mode
Zero
Zero
-
(Bytes)
Size
1
1
2
2
0
Notes
0x02
Bit 0: Reserved. Must be 0b
Bit 1: If 0b, update the EEPROM RNG seed register prior to random number
Bit 2: If 0b, then return the random number. Do not change the
Bits 3 to 7: Reserved. Must be 0b
Always 0x0000
Always 0x0000
generation
If 1b, generate random number using the existing RNG seed
nonce.
If 1b, then store the first 12 bytes of the random number in
the nonce register and return the 16 byte random number
(1)
Atmel ATAES132 Preliminary Datasheet
8760A−CRYPTO−5/11
62