AT45DB321D-TU Atmel, AT45DB321D-TU Datasheet - Page 2

• Manufacturer Part Number: AT45DB321D-TU
• Description: IC FLASH 32MBIT 66MHZ 28TSOP
• Manufacturer: Atmel

Specifications of AT45DB321D-TU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (8192 pages x 528 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSOP
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 528 B x 8192
• Memory Configuration: 8192 Pages X 528 Bytes
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. Pin Configurations and Pinouts
2
Figure 2-1.
Note:
Figure 2-3.
1. The metal pad on the bottom of the MLF
AT45DB321D
RESET
package is floating. This pad can be a “No
Connect” or connected to GND.
SCK
C
D
A
B
E
CS
SI
MLF
BGA Package Ball-Out (Top View)
NC
NC
NC
NC
1
2
3
4
1
(1)
SCK
NC
CS
SO
NC
2
(VDFN) Top View
RDY/BSY
GND
NC
NC
3
SI
sequentially access its data. The simple sequential access dramatically reduces active pin
count, facilitates hardware layout, increases system reliability, minimizes switching noise, and
reduces package size. The device is optimized for use in many commercial and industrial appli-
cations where high-density, low-pin count, low-voltage and low-power are essential.
To allow for simple in-system reprogrammability, the AT45DB321D does not require high input
voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for
both the program and read operations. The AT45DB321D is enabled through the chip select pin
(CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output
(SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
RESET
VCC
WP
NC
NC
4
NC
NC
NC
NC
NC
5
8
7
6
5
SO
GND
VCC
WP
Figure 2-2.
Figure 2-4.
Note:
RDY/BUSY
RESET
GND
VCC
SCK
WP
NC
NC
NC
NC
NC
CS
SO
SI
TSOP package is not recommended for new designs. Future die
shrinks will support 8-pin packages only.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SOIC Top View
TSOP Top View: Type 1
RESET
SCK
CS
SI
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
3597O–DFLASH–10/09
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC