AT45DB321D-TU Atmel, AT45DB321D-TU Datasheet - Page 32

• Manufacturer Part Number: AT45DB321D-TU
• Description: IC FLASH 32MBIT 66MHZ 28TSOP
• Manufacturer: Atmel

Specifications of AT45DB321D-TU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (8192 pages x 528 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSOP
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 528 B x 8192
• Memory Configuration: 8192 Pages X 528 Bytes
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16. Power-on/Reset State
16.1
17. System Considerations
32
Initial Power-up/Reset Timing Restrictions
AT45DB321D
When power is first applied to the device, or when recovering from a reset condition, the device
will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a
high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode
3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive
clock state.
At power up, the device must not be selected until the supply voltage reaches the V
further delay of t
reset mode until the V
operations are disabled and the device does not respond to any commands. After power up is
applied and the V
before the device can be selected in order to perform a read operation.
Similarly, the t
value (V
power-up, the device will default in Standby mode.
The RapidS serial interface is controlled by the clock SCK, serial input SI and chip select CS
pins. These signals must rise and fall monotonically and be free from noise. Excessive noise or
ringing on these pins can be misinterpreted as multiple edges and cause improper operation of
the device. The PC board traces must be kept to a minimum distance or appropriately termi-
nated to ensure proper operation. If necessary, decoupling capacitors can be added on these
pins to provide filtering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A
key element of any voltage regulation scheme is its current sourcing capability. Like all Flash
memories, the peak current for DataFlash occur during the programming and erase operation.
The regulator needs to supply this peak current requirement. An under specified regulator can
cause current starvation. Besides increasing system noise, current starvation during program-
ming or erase can lead to improper operation and possible data corruption.
Symbol
t
t
V
VCSL
PUW
POR
POR
) before the device can perform a write (Program or Erase) operation. After initial
Parameter
V
Power-Up Device Delay before Write Allowed
Power-ON Reset Voltage
CC
PUW
VCSL
(min.) to Chip Select low
CC
delay is required after the V
. During power-up, the internal Power-on Reset circuitry keeps the device in
is at the minimum operating voltage V
CC
rises above the Power-on Reset threshold value (V
CC
rises above the Power-on Reset threshold
Min
1.5
CC
70
(min.), the t
Typ
VCSL
POR
3597O–DFLASH–10/09
delay is required
Max
). At this time, all
2.5
20
CC
(min.) and
Units
ms
µs
V