AT45DB321D-TU Atmel, AT45DB321D-TU Datasheet - Page 25

• Manufacturer Part Number: AT45DB321D-TU
• Description: IC FLASH 32MBIT 66MHZ 28TSOP
• Manufacturer: Atmel

Specifications of AT45DB321D-TU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 32M (8192 pages x 528 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSOP
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 528 B x 8192
• Memory Configuration: 8192 Pages X 528 Bytes
• Clock Frequency: 20MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. “Power of 2” Binary Page Size Option
13.1
3597O–DFLASH–10/09
Programming the Configuration Register
“Power of 2” binary page size Configuration Register is a user-programmable nonvolatile regis-
ter that allows the page size of the main memory to be configured for binary page size
(512 bytes) or DataFlash standard page size (528 bytes). The “power of 2” page size is a one-
time programmable configuration register and once the device is configured for “power
of 2” page size, it cannot be reconfigured again. The devices are initially shipped with the
page size set to 528 bytes. The user has the option of ordering binary page size (512
bytes) devices from the factory. For details, please refer to
page
For the binary “power of 2” page size to become effective, the following steps must be followed:
If the above steps are not followed to set the page size prior to page programming, incorrect
data during a read operation may be encountered.
To program the Configuration Register for “power of 2” binary page size, the CS pin must first be
asserted as it would be with any other command. Once the CS pin has been asserted, the
appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The
4-byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H. After the
last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate
the internally self-timed program cycle. The programming of the Configuration Register should
take place in a time of t
busy. The device must be power cycled after the completion of the program cycle to set the
“power of 2” page size. If the device is powered-down before the completion of the program
cycle, then setting the Configuration Register cannot be guaranteed. However, the user should
check bit 0 of the status register to see whether the page size was configured for binary page
size. If not, the command can be re-issued again.
Figure 13-1. Erase Sector Protection Register
Command
Power of Two Page Size
1. Program the one-time programmable configuration resister using opcode sequence
2. Power cycle the device (i.e. power down and power up again).
3. The page for the binary page size can now be programmed.
48.
3DH, 2AH, 80H and A6H (please see
CS
SI
Each transition
represents 8 bits
P
, during which time the Status Register will indicate that the device is
Opcode
Byte 1
Opcode
Byte 2
Section
Byte 1
13.1).
3DH
Opcode
Byte 3
Section 26. ”Ordering Information” on
Byte 2
Opcode
2AH
Byte 4
AT45DB321D
Byte 3
80H
Byte 4
A6H
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