AT45DB642D-CNU Atmel, AT45DB642D-CNU Datasheet - Page 11

• Manufacturer Part Number: AT45DB642D-CNU
• Description: IC FLASH 64MBIT 66MHZ 8CASON
• Manufacturer: Atmel

Specifications of AT45DB642D-CNU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 66MHz
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-CASON
• Package: 8CASON
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256KByte x 32
• Timing Type: Synchronous
• Interface Type: Parallel|Serial-SPI
• Data Bus Width: 8 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 256 KB x 32
• Ic Interface Type: Parallel, Serial
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.7V To 3.6V
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.6
Table 7-2.
7.7
3542K–DFLASH–04/09
PA12/
A22
0
0
0
0
1
1
1
1
•
•
•
Sector Erase
Chip Erase
PA11/
A21
0
0
0
0
1
1
1
1
•
•
•
Sector Erase Addressing
PA10/
A20
0
0
0
0
1
1
1
1
•
•
•
(1)
The Sector Erase command can be used to individually erase any sector in the main memory.
There are 32 sectors and only one sector can be erased at one time. To perform sector 0a or
sector 0b erase for the standard DataFlash page size (1056 bytes), an opcode of 7CH must be
loaded into the device, followed by three address bytes comprised of 10 page address bits
(PA12 - PA3) and 14 don’t care bits. To perform a sector 1-31 erase, the opcode 7CH must be
loaded into the device, followed by three address bytes comprised of 5 page address bits (PA12
- PA8) and 19 don’t care bits. To perform sector 0a or sector 0b erase for the binary page size
(1024 bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes
comprised of 1 don’t care bit and 10 page address bits (A22 - A13) and 13 don’t care bits. To
perform a sector 1-31 erase, the opcode 7CH must be loaded into the device, followed by three
address bytes comprised of 1 don’t care bit and 5 page address bits (PA12 - PA8) and 18 don’t
care bits. The page address bits are used to specify any valid address location within the sector
which is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the
selected sector. The erase operation is internally self-timed and should take place in a maximum
time of t
is busy.
The entire main memory can be erased at one time by using the Chip Erase command.
To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, 80H and 9AH
must be clocked into the device. Since the entire memory array is to be erased, no address
bytes need to be clocked into the device, and any data clocked in after the opcode will be
ignored. After the last bit of the opcode sequence has been clocked in, the CS pin can be deas-
serted to start the erase process. The erase operation is internally self-timed and should take
place in a time of t
The Chip Erase command will not affect sectors that are protected or locked down; the contents
of those sectors will remain unchanged. Only those sectors that are not protected or locked
down will be erased.
PA9/
A19
0
0
0
1
0
0
1
1
•
•
•
SE
PA8/
. During this time, the status register and the RDY/BUSY pin will indicate that the part
A18
0
0
1
0
0
1
0
1
•
•
•
CE
PA7/
A17
X
X
X
X
X
X
0
0
•
•
•
. During this time, the Status Register will indicate that the device is busy.
PA6/
A16
X
X
X
X
X
X
0
0
•
•
•
PA5/
A15
X
X
X
X
X
X
0
0
•
•
•
PA4/
A14
X
X
X
X
X
X
0
0
•
•
•
PA3/
A13
X
X
X
X
X
X
0
1
•
•
•
PA2/
A12
X
X
X
X
X
X
X
X
•
•
•
PA1/
A11
X
X
X
X
X
X
X
X
•
•
•
PA0/
A10
X
X
X
X
X
X
X
X
•
•
•
Sector
0a
0b
28
29
30
31
1
2
•
•
•
11