AT45DB642D-CNU Atmel, AT45DB642D-CNU Datasheet - Page 25

• Manufacturer Part Number: AT45DB642D-CNU
• Description: IC FLASH 64MBIT 66MHZ 8CASON
• Manufacturer: Atmel

Specifications of AT45DB642D-CNU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 66MHz
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-CASON
• Package: 8CASON
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256KByte x 32
• Timing Type: Synchronous
• Interface Type: Parallel|Serial-SPI
• Data Bus Width: 8 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 256 KB x 32
• Ic Interface Type: Parallel, Serial
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.7V To 3.6V
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. “Power of 2” Binary Page Size Option
13.1
14. Manufacturer and Device ID Read
3542K–DFLASH–04/09
Programming the Configuration Register
“Power of 2” binary page size Configuration Register is a user-programmable nonvolatile regis-
ter that allows the page size of the main memory to be configured for binary page size
(1024 bytes) or standard DataFlash page size (1056 bytes). The “power of 2” page size is a
one-time programmable configuration register and once the device is configured for
“power of 2” page size, it cannot be reconfigured again. The devices are initially shipped
with the page size set to 1056 bytes. The user has the option of ordering binary page size (1024
bytes) devices from the factory. For details, please refer to
page
For the binary “power of 2” page size to become effective, the following steps must be followed:
If the above steps are not followed in setting the the page size prior to page programming, user
may expect incorrect data during a read operation.
To program the Configuration Register for “power of 2” binary page size, the CS pin must first be
asserted as it would be with any other command. Once the CS pin has been asserted, the
appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The 4-
byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H. After the
last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate
the internally self-timed program cycle. The programming of the Configuration Register should
take place in a time of t
busy. The device must be power-cycled after the completion of the program cycle to set the
“power of 2” page size. If the device is powered-down before the completion of the program
cycle, then setting the Configuration Register cannot be guaranteed. However, the user should
check bit 0 of the status register to see whether the page size was configured for binary page
size. If not, the command can be re-issued again.
Figure 13-1. Erase Sector Protection Register
Identification information can be read from the device to enable systems to electronically query
and identify the device while it is in system. The identification method and the command opcode
comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI
Compatible Serial Interface Memory Devices”. The type of information that can be read from the
Command
Power of Two Page Size
1. Program the one-time programmable configuration resister using opcode sequence
2. Power cycle the device (i.e. power down and power up again).
3. User can now program the page for the binary page size.
51.
3DH, 2AH, 80H and A6H (please see
SI or IO
7
- IO
CS
0
P
, during which time the Status Register will indicate that the device is
Each transition
represents 8 bits
Opcode
Byte 1
Section
Opcode
Byte 2
Byte 1
13.1).
3DH
Opcode
Byte 3
Section 27. ”Ordering Information” on
Byte 2
2AH
Opcode
Byte 4
Byte 3
80H
Byte 4
A6H
25