AT45DB642D-CNU Atmel, AT45DB642D-CNU Datasheet - Page 7

• Manufacturer Part Number: AT45DB642D-CNU
• Description: IC FLASH 64MBIT 66MHZ 8CASON
• Manufacturer: Atmel

Specifications of AT45DB642D-CNU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 66MHz
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-CASON
• Package: 8CASON
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256KByte x 32
• Timing Type: Synchronous
• Interface Type: Parallel|Serial-SPI
• Data Bus Width: 8 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 256 KB x 32
• Ic Interface Type: Parallel, Serial
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.7V To 3.6V
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2
6.3
3542K–DFLASH–04/09
Continuous Array Read (High Frequency Mode: 0BH): Up to 66 MHz
Continuous Array Read (Low Frequency Mode: 03H): Up to 33 MHz
The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached during a
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one page
to the beginning of the next page). When the last bit (or byte if using the 8-bit interface mode) in
the main memory array has been read, the device will continue reading back at the beginning of
the first page of memory. As with crossing over page boundaries, no delays will be incurred
when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Continuous Array
Read is defined by the f
fers and leaves the contents of the buffers unchanged.
This command can be used with the serial interface to read the main memory array sequentially
in high speed mode for any clock frequency up to the maximum specified by f
continuous read array with the page size set to 1056 bytes, the CS must first be asserted then
an opcode 0BH must be clocked into the device followed by three address bytes and a dummy
byte. The first 13 bits (PA12 - PA0) of the 24-bit address sequence specify which page of the
main memory array to read, and the last 11 bits (BA10 - BA0) of the 24-bit address sequence
specify the starting byte address within the page. To perform a continuous read with the page
size set to 1024 bytes, the opcode, 0BH, must be clocked into the device followed by three
address bytes (A22 - A0) and a dummy byte. Following the dummy byte, additional clock pulses
on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous
Array Read is defined by the f
data buffers and leaves the contents of the buffers unchanged.
This command can be used with the serial interface to read the main memory array sequentially
without a dummy byte up to maximum frequencies specified by f
read array with the page size set to 1056 bytes, the CS must first be asserted then an opcode,
03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit
page and byte address sequence). The first 13 bits (PA12 - PA0) of the 24-bit address sequence
specify which page of the main memory array to read, and the last 11 bits (BA10 - BA0) of the
24-bit address sequence specify the starting byte address within the page. To perform a contin-
uous read with the page size set to 1024 bytes, the opcode, 03H, must be clocked into the
device followed by three address bytes (A22 - A0). Following the address bytes, additional clock
pulses on the SCK pin will result in data being output on the SO (serial output) pin.
CAR1
specification. The Continuous Array Read bypasses both data buf-
CAR1
specification. The Continuous Array Read bypasses both
CAR2
. To perform a continuous
CAR1
. To perform a
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