AT45DB642D-CNU Atmel, AT45DB642D-CNU Datasheet - Page 24

• Manufacturer Part Number: AT45DB642D-CNU
• Description: IC FLASH 64MBIT 66MHZ 8CASON
• Manufacturer: Atmel

Specifications of AT45DB642D-CNU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 66MHz
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-CASON
• Package: 8CASON
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256KByte x 32
• Timing Type: Synchronous
• Interface Type: Parallel|Serial-SPI
• Data Bus Width: 8 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 256 KB x 32
• Ic Interface Type: Parallel, Serial
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.7V To 3.6V
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12. Deep Power-down
12.1
24
Resume from Deep Power-down
AT45DB642D
After initial power-up, the device will default in standby mode. The Deep Power-down command
allows the device to enter into the lowest power consumption mode. To enter the Deep Power-
down mode, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode
of B9H command must be clocked in via input pins (SI or IO
mand has been clocked in, the CS pin must be de-asserted to initiate the Deep Power-down
operation. After the CS pin is de-asserted, the will device enter the Deep Power-down mode
within the maximum t
instructions are ignored except for the Resume from Deep Power-down command.
Figure 12-1. Deep Power-down
The Resume from Deep Power-down command takes the device out of the Deep Power-down
mode and returns it to the normal standby mode. To Resume from Deep Power-down mode, the
CS pin must first be asserted and an opcode of ABH command must be clocked in via input pins
(SI or IO
asserted to terminate the Deep Power-down mode. After the CS pin is de-asserted, the device
will return to the normal standby mode within the maximum t
high during the t
Deep Power-down, the device will return to the normal standby mode.
Figure 12-2. Resume from Deep Power-Down
Command
Deep Power-down
Command
Resume from Deep Power-down
7
-IO
0
). After the last bit of the command has been clocked in, the CS pin must be de-
RDPD
EDPD
time before the device can receive any commands. After resuming form
SI or IO
SI or IO
time. Once the device has entered the Deep Power-down mode, all
7
7
- IO
- IO
CS
CS
0
0
Serial/8-bit
Each transition
represents 8 bits
Each transition
represents 8 bits
Both
Serial/8-bit
Both
Opcode
Opcode
RDPD
7
-IO
0
). After the last bit of the com-
time. The CS pin must remain
Opcode
B9H
Opcode
3542K–DFLASH–04/09
ABH